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| copyright ? mediatek inc. all rights reserved. MT6516 design notice v1.0 MT6516 design notice v1.0 2009 / april wcp/sa free datasheet http://www.datasheet-pdf.com/
copyright ? mediatek inc. all rights reserved. 2 change notice change notice ? 2009/05/11 initial document ? 2009/06/22 add iq 510ohm free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 3 outline outline ? MT6516 main features & package ? design notice ? MT6516 schematic design notice ? pmic mt6326 design notice ? audio part design notice ? speech part design notice ? camera design notice ? display design notice ? ddr memory layout rule ? usb 2.0 high speed design notice ? factory mode and engineer mode ? download and meta link ? MT6516 memory support plan ? appendix - peripherals design notice ? wifi/bt co-module application note ? mt3326 gps application note ? dtv part design note ? fm design notice free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 4 ? separate application (a rm9) and hard real-time modem (arm7) ? multi-cores with hw coprocessors soc ? application: arm926ejs 416mhz ? modem: arm7 (52mhz/104mhz) + 2 dsp(104mhz) ? ceva dsp (312mhz) for video and unpredictable multimedia application on smartphone ? 65nm process. ultra low power design. ? graphics, display, image, camera, video multimedia hardware accelerators . ? 2d graphics - support window mobile bitblt function ? 3d graphics - support opengl es 1.1 common/common lite profile ? 3d performance: fill rate = 32m, triangle rate = 3.7m ? wide range of resolution up to wvga size ? various display interface support ? 8080 host if (mipi dbi) ? 8/9/16/32-bit serial if ? rgb interface (mipi dpi) ? mipi dsi interface ? high performance memory controller @ 104mhz, support ? 32-bit / 16-bit lp-ddr sdram ? 4 chip selects : support up to 4 dram devices ? nand-boot supported ? nand data storage supported ? peripherals ?dual sim ? 3 x sdio, 3 x i2c, 1 x i2s, 4 x uart ? 1-wire interface, 7 x pwm ? 8 x 8 key matrix ? touch panel interface ? usb 2.0 high speed integrate with phy . MT6516 main feature MT6516 main feature free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 5 MT6516 design package building blocks MT6516 design package building blocks mcp memory 1g ddr 2g nand 2.8 6? lcd qvga camera 5mp autofocus t-flash card mt6140d+sky77344 edge transceiver mt5151 dtv receiver mt3326 gps receiver mt6611 & mt5921 wifi/bt co-module apps. processor arm926ejs 416mhz modem mcu arm7 104mhz multimedia asic ar1000 fm mt6326 pmic ti bq27500 smart battery (optional) sim interface (dual sim capable) uart sdio uart sdio bpi i2c i2c parallel camera i/f emi nfi i2c sdio lcm i/f 2d 3d 3d scaler mp3 h.264 jpeg codec internal memory free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 6 MT6516 package MT6516 package 0.26 0.21 1.2 0.3 0.378 / 0.535 564 15 15 c a1 a (max.) b e1 / e2 n e d substrate thk. stand off package thk. ball dia. ball pitch ball count body size table 1 definition of tfbga 15mm*15mm, 564-ba ll, 0.378 mm pitch package (unit: mm) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. design notice design notice - - mt6 mt6 516 schematic design notice 516 schematic design notice copyright ? mediatek inc. all rights reserved. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 8 schematic notice (1/7): boot schematic notice (1/7): boot - - up selection up selection h( dvdd )l(gnd) ionejtag enable one jtag functio n disable iboot boot from external memo r boot from bootrom secu_en enable secure booting disable iadmux admux memory device ad-demux memory device icoresight coresight enable, coresight disable fsource burn efuse normal 1 j o ) = - MT6516 currently only support ddr memory, so this selection always choose gnd connect fsource to gnd by 0ohm, otherwise the uuid number will be unstable. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 9 schematic notice (2/7) schematic notice (2/7) the avdd power must follow the connection show above to avoid the influence between afe, rfe and mbuf free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 10 schematic notice (3/7) schematic notice (3/7) connect au_vcm_no to gnd add 2 capacitors (1uf, 0.1uf) in avdd12_pll free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 11 c504 1u v t503 m1005c080mtacb v t505 m1005c080mtacb v t504 m1005c080mtacb v t506 m1005c080mtacb v t507 m1005c080mtacb r507 47k r502 47k r504 47k r503 47k r505 47k r506 47k v t501 m1005c080mtacb v t502 m1005c080mtacb mcda3 1 mcda1 1 mccm0 1 mcck 1 mcda0 1 mcda2 1 j501 sd_card_socket (skt sd/mmc standard ty tf_5015880801-a dat2 1 cd/dat3 2 cmd 3 vdd 4 clk 5 vss2 6 dat0 7 dat1 8 shield 11 shield 10 shield 12 shield 9 vdd ?for better interoperability and stability, please reserve 47k ohm in each memory card interface line. schematic notice (4/7) schematic notice (4/7) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 12 schematic notice (5/7) schematic notice (5/7) add a diode between MT6516 pwr_key and mt6326 pwrkey MT6516 mt6326 pmic power key bottom add a diode and a eint to mt6326 pwrkey add a 1k resistor to avoid esd damage. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 13 u100e tk65_18 MT6516-564/p0.53/b0.27(15x15)/iac jtrst_b ad34 jtck ad38 jtdi ab36 jtms ac33 jtdo ac35 jrtck ab34 j2trst_b am32 j2tck ak30 j2tdi an33 j2tms ap34 j2tdo ar35 j2rtck al31 ionejtag t38 jztrst_b 16 jztdo 16 jztms 16 jztdi 16 jztck 16 jtdi 16 jtdo 16 jtck 16 jzrtck 16 jtms 16 jrtck 16 jtrst_b 16 ionejtag 16 schematic notice (6/7) :debug port schematic notice (6/7) :debug port arm9 (ap side) jtag arm7 (modem side) jtag use only one jtag to cont rol ap and modem side mcu free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 14 schematic notice (7/7) : nfi interface schematic notice (7/7) : nfi interface ? to support 1.8 v nand mcp, you need to ? connect vdd33_lcd of bb part to 1.8 v ? check if lcm module io can support 1. 8v first. connect lcm io power pin (vddio) to 1.8 v (see lcm selection guide to 1.8 v lcm section) bb bb 1 1 lcm io lcm io 2 2 ? beware that nand flash , parallel lcm , and vdd33_nld must use same power domain ! free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 15 rf iq connection ( remember add 510ohm rf iq connection ( remember add 510ohm between baseband and mt6140d) between baseband and mt6140d) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 16 reset button design suggestion reset button design suggestion 1. basically, the MT6516 phone don?t need reset button. (users remove battery when system hang) 2. there are two kinds of suggestion design of reset button. 1. only add a pull low button on sysrst_b pin 1. advantage : cost effective 2. disadvantage : user must press pwrkey to restart system 2. add a reset chip on pwrkey pin and sysrst_b pin. 1. advantage : user can press reset then direct restart the phone. 2. disadvantage : need a extra reset chip pwrkey sw702 ksw 1 2 sysrst_b reset chip reset chip that only generate one pulse sw702 ksw 1 2 sysrst_b free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 17 default uart dispatch notice default uart dispatch notice uart1 uart3 usb port copy here uart2 uart4 download bootloader , meta link, production line test point user define, de fault use for agps user define, de fault use for bluetooth data log for debugging, boot-up selection and setting. modem side meta link . download image bin file , active sync, mass storage, rndis free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 18 reference power distribution reference power distribution vdd33 vdd33_tracer vdd33_mipi/mipi_tx/mipi_rx vdd33_i2c (camera) vdd33_mc0/1/2 vdd33_nld vdd33_spi vdd33_emi (6 balls) avdd30_vsim avdd30_vsim2 avdd33_usb avdd12_usb vcore 1.3v vdd 2.8v vsdio vm 1.8v vsim vgp vusb 3.3v vcam_a vddk (52 balls) vdd33_camera ? mt6326 ? MT6516 core power usb core power general io etm io mipi power spi power nand/lcm power emi power (lpddr) camera i/o power scl1/sda1 power sim1 power sdio1/sdio2/sdio3 power sim2 power usb phy power free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 19 MT6516 reference phone pcb layer define MT6516 reference phone pcb layer define - b z f s / p / b n f ` % f g j o f . b u f s j b m 4 v h h f t u j p o % j f $ p o t v h h f t u u i j d l o f t t n j m 7 j b c c c soldermask soldermask c c 0.4 c c c add plating plating 1comp(l1) c 3 ' 5 s b d f copper foil 0.5 oz h oz+plating c 1.4 c c c c pp pp 1080 65% 4.3 2.82 2l2 c 4 j h o b m copper foil 1.0 oz 0.50 oz+plating c 1.3 c c c c core pp 1080 65% 4.3 2.82 3l3 c ( / % copper foil 1.0 oz copper 1.0 oz c 1.3 c c c c pp fr-4 core 4mil 4.3 4 4l4 c 3 ' 5 s b d f copper foil 1.0 oz copper 1.0 oz c 1.3 c c c c core pp 7628 50% 4.3 8.38 5l5 c ( / % copper foil 1.0 oz copper 1.0 oz c 1.3 c c c c pp fr-4 core 4mil 4.3 4 6l6 c 4 j h o b m copper foil 1.0 oz copper 1.0 oz c 1.3 c c c c core pp 1080 65% 4.3 2.82 7l7 c 4 j h o b m copper foil 1.0 oz 0.50 oz+plating c 1.3 c c c c pp pp 1080 65% 4.3 2.82 8sold(l8) c 3 ' 5 s b d f copper foil 0.5 oz c c c add plating plating h oz+plating c 1.4 c c c soldermask soldermask c c 0.4 board thickness =1.00mm +/- 10%mm c c c c c 39.06 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. mt6326 pmic design notice mt6326 pmic design notice copyright ? mediatek inc. all rights reserved. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 21 mt6326 pmic mt6326 pmic base band processor 2g transceiver memory ram flash boost converter 1. back light 2. flash light 3. usb otg kp led driver (open drain) vibrator driver (open drain) class-d audio amplifier 1 wifi bluetooth camera sensor (af) audio switch charger controller reset generator i2c m 1 2 3 4 5 6 7 8 9 0 # lcm module usb device sim1 class-d audio amplifier 2 essential ldos va vio vrtc1 vrtc2 vsim1 vgp2 2 dc-dc (for vcore) dvfs dc-dc (for vmem) 2g transceiver ldos vrf, vtcxo basic feature ldos vusb, vbt vcam_d vcam_a extra ldos wifi general purpose vcore2 1.2(0.9_1.8v(1.5)/600ma vm 1.8_2.8v/600 ma vio_2.8v/150ma va_2.8v/150ma vrtc1_2.8v/2ma vusb 3.3v/100ma vbt 2.8_3v/100ma vcam_d 1.3_1.5_1.8_2.8v/100ma vcam_a 1.8_2.5_2.8v/250ma vrf 2.8v/250ma vtcxo 2.8v/50ma vrtc2_1.2_1.5v/0.1ma backup battery vwifi2v8 2.8_3_3.3v/150ma vwifi3v3 2.8_3_3.3v/300ma mt6326 control 3g transceiver ldos vpa 1.3~3.4v/600ma 3g pa analog switch sdio device vsdio 2.8_3.3v/350ma 3g transceiver v3grx 2.8_3_3.3v/100ma v3gtx 2.8_3_3.3v/200ma dc-dc (for 3g pa) pmos +rsense charger in current sink *8 (current sharing) (mux) vcore1 1.2(0.9_1.8v(1.5)/600ma 2-in-1 receiver vgp1 1.8/2.8/100ma sim2 vsim1 1.8_3v/100ma vsim2 1.8_3v/100ma free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 22 mt6326 pmic ldo mt6326 pmic ldo re gulator output voltage output curre nt output compone nts note s vcore 0.9~1.35 1.8 600 2.2uh + 4.7uf max. output current = 100ma when set to < 1.1v vcore 2 0.9~1.35 1.8 600 2.2uh + 4.7uf max. output current = 100ma when set to < 1.1v vm 1.8 2.8 600 2.2uh + 4.7uf max. output current = 450ma when set to 2.8v v3gpa 1.3~3.4 600 2.2uh + 4.7uf vbat should keep 600mv higher than v3gpa to keep good regulation. v3gtx 2.5/2.8/3/3.3 200 4.7uf v3grx 2.5/2.8/3/3.3 100 4.7uf vrf 2.8 250 4.7uf vtcxo 2.8 50 1uf va 2.8 150 4.7uf ' p s " 7 % % ' . q p x f s s f r v j s f n f o u vcama 1.5/1.8/2.5/2.8 250 4.7uf vwifi3v3 2.5/2.8/3/3.3 300 4.7uf vwifi2v8 2.5/2.8/3/3.3 150 4.7uf vio 2.8 150 1uf ' p s 7 % % b o e q f s j q i f s b m * 0 s f r v j s f n f o u vsim 1.8/3.0 100 1uf vusb 3.3 100 1uf vbt 1.3/1.5/1.8/2.5/2.8/3.0/3.3 100 1uf vcamd 1.3/1.5/1.8/2.5/2.8/3.0/3.3 100 1uf vsdio 2.8/3 300 4.7uf vgp1 1.3/1.5/1.8/2.5/2.8/3.0 100 1uf vgp2 1.3/1.5/ 1.8 /2.5 2.8/3.0 100 1uf vrtc 1.5/1.2 0.1 1uf bat_backup 2.8 2 1uf # b d l v q c b u u f s z free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 23 vbat input filter vbat input filter ? vbat input should reserve enough filt er to prevent interference to rf performance. ? all above component should be as close to mt6326 ic as possible in red frame , all co mponent should be in shielding case. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 24 class class - - d audio amplifier output filter d audio amplifier output filter ? reserve 2 stage filter at output stage of class-d to prevent interference to rf performance. ? 1 st stage filter should be close to ic, 2 nd stage filter should be close to loud speaker. ? all the traces from ic to 2 nd stage filter should not exposed to prevent interference to rf performance. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 25 class class - - d : 2 d : 2 - - in in - - 1 receiver function 1 receiver function ? mt6326 has 2 in 1 receiver function , when use external amplifier , must connect recin_p and recin_n. ? the typical value of r1 and r2 are 20 ohm each , and suggest r3 and r4 to be 4 ohm (32?20?8=4) ? due to value variation of r1 and r2 are higher , so maybe suffer audio volume. r1 r2 r3 r4 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 26 class class - - d : audio amplifier power output d : audio amplifier power output ? although mt6326 class-d power output is 1w at 8 ? , because congenital power source limitation is 4.2v from vbat , but compare with other discrete amplifiers , mt6326 equal other amplifier in performance. ti poutput profile free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 27 boost1 for parallel backlight lcm or other 5v boost1 for parallel backlight lcm or other 5v requirement requirement ? reserve filter at input/output to prevent interference to rf performance. ? l200/l201/c205/c279 should be in shield case and close near mt6326 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 28 boost2 for serial backlight lcm boost2 for serial backlight lcm ? reserve discrete b/l driver to prevent any improper design causing interference to rf performance. in this red frame, all components are reserved only. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 29 ic protection: pwrkey and bat_on ic protection: pwrkey and bat_on please reserve 1k resist or on phone pcb to protect pwrkey no matter if pwrkey connect to any i/o connector or not. please reserve 1k resistor on phone pcb to protect bat_on pin if bat_on is used to detect battery. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 30 ic protection: vbat ic protection: vbat i/o cable mt6326 power supply phone v- v+ gnd vbat reserve 1. 22uf capacitor 2. zener diode on phone. reserve 1000uf or above capacitor at the output of power supply, and at the end of connector cable. mt6326 has lower vbat voltage ra ting. (max. 4.3v.) some pro tection should reserve to prevent the damage by voltage surge. ?design notice in phone side: 1. at least 22uf capacitor. 2. add zener diode (5.1v) to pro tect the ic against low freq uency voltage s urge. put it between battery c onnector and mt6326. notice: if using io connector or test point to supply vbat for download, m anufacture, or repair, should let vbat trac e passing zener diode and 22uf capacitor bef ore entering ic. notice: using 5.1v zener will introduce some leakage when vbat = 4.2v. ?design notice in power supply side: add 1000uf (or above) capac itor at the output of the power supply to reduce the voltage bounce caused by long power cable. and the power cable s hould be as shor t as possible. also add 1000uf (or above) capacitor at the end of power cable (near phone side). free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 31 ic protection: chrin ic protection: chrin 7v 9v mt6223/35/38 /mt6326 6.8v 9v charger ovp point 30v 15v max. charger input external ovp/ocp mt6305 /mt6318 vchg r201 0 u202 bq24316 1 2 7 8 3 4 5 6 in vss ilim out nc /fault /ce vbat vbat to chrin c235 1u (16v 0805) chrin r202 220k r205 25k c205 1uf f201 fuse(1a 0603) external ovp/ocp: nc notice : you can get better ch arger protection by using external ovp/ocp device. ovp/ocp qualified vendor : 1. ti ? bq24314 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 32 ic protection: ovp + charger ic protection: ovp + charger 7v 9v mt6223/35/38 /mt6326 6.17v(apl3206) 6.8v(apl3206a) 9v charger ovp point 30v 15v max. charger input external ovp/ocp mt6305 /mt6318 ovp/ocp + charger qualified vendor : 1. anpec - apl3206 qbi external ovp + charger : notice : you can get better ch arger protection by using external ovp/ocp device. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 33 bypass capacitor: bypass capacitor: vcore vcore and vm and vm ? reserve enough bypass capacitors both at vcore and vm to obtain good system stability. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 34 dvdd12_mipi power connection dvdd12_mipi power connection ? mt6326 vcore1 default is 1.3v , and mipi_1.2v power spec. is 1.1~1.3v , so if need to use mi pi could connect vcore2(if not used). besides , must add external ldo for mipi_1.2v. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 35 bypass capacitor: bypass capacitor: layout rule for vcore ? due to MT6516 have many vcore ( vddk) balls , and these balls scatter around package of MT6516. please put bypass capacitor around MT6516 to increase system reliably. current source current source current source current source free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 36 bypass capacitor: avdd and vdd bypass capacitor: avdd and vdd ? reserve required input filter for abb as specified in left schematics. ? avdd28_mbuf suggest to connect to vtcxo. ? reserve 1uf for i/o power input. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 37 layout notice: charging path layout notice: charging path ? charging related component (u204, rsense, r219) should be close to battery connector. ? minimum trace width are ma rked on the schematics above. ? isense and batsns should be connected as the figure above. ? the trace from rsense to battery c onnector (marked in red) should not share with other vbat traces. ? isense/batsns should be routed as differential traces which are away from noisy signals. f200 fuse(1a 0603) 40mil isense batsns chrin gatdrv vbat rsense 0.2 6mil r219 10k u204 apl3206 qbi acin 1 acin 2 out 7 out 8 gnd 3 vbat 4 gatdrv 5 chrin 6 ep 9 6mil vchg 6mil 6mil 6mil 40mil 40mil 40mil free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 38 ? the exposed pad of the charger ovp ic should connect to a large copper ground plane to get good thermal performance. ? the exposed pad should has at l east 6 gnd via connecting to inner layer. exposed pad to a large copper ground f200 fuse(1a 0603) 40mil isense batsns chrin gatdrv vbat rsense 0.2 6mil r219 10k u204 apl3206 qbi acin 1 acin 2 out 7 out 8 gnd 3 vbat 4 gatdrv 5 chrin 6 ep 9 6mil vchg 6mil 6mil 6mil 40mil 40mil 40mil layout notice: charger ovp ic layout notice: charger ovp ic free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 39 layout notice: vbat traces layout notice: vbat traces ? the vbat for the 5 blocks show a bove (class-d, buck converter, boost1, boost2 converter and analog ldos) should star-connect to the bulk capacitor near battery connector. class-d buck converter analog ldos boost1 converter boost2 converter free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 40 layout notice: vbat traces layout notice: vbat traces rf pa boost2 class-d amplifier charging path buck and boost converters bulk capacitor near battery connector analog ldos ? star-connect different vbat group to battery connector directly free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 41 class class - - d gnd d gnd ? the gnd for class-d should isolated carefully. l1 l2 l3 l4 l5 l6 l7 l8 gnd merge, other gnd (mark by black) should be isolate. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 42 layout notice: gnd_vref traces layout notice: gnd_vref traces ? vref capacitor (1uf) should be close to ic. ? gnd_vref (gnd for vref) should isolate carefully. pin67 (gnd_vref) capacitor for vref the trace should connect to gnd of battery connector the trace should isolated and protected by gnd free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 43 ? the output trace (marked in above schematics) should be differential, and protected by gnd. ? 1 st filter should be as close to ic as possible. (as the left figure showed.) ? the trace width should be ? 8 ohm speaker: 25 mil. ? 4 ohm speaker: 40 mil. layout notice: class layout notice: class - - d output d output free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 44 ? components should be as close to ic as possible. ? l200/d200/l201/c205/d200/c208 should be close and parallel to each other. ? the direction of l200/d200 should arrange as the arrowhead in left figure. ? must add d204 to prevent feedback of vbus when turn off boost1. layout notice: boost1 layout notice: boost1 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. mt6 mt6 516 design notice (audio) 516 design notice (audio) copyright ? mediatek inc. all rights reserved. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 46 outline outline ? analog gain setting ? rc value ? pcb layout ? audio feature ? mp3 decoder ? 3d surround effect ?eq 2.0 ? audio agc ? audio compensation filter ? for audio features, please refer to ? l1_audio_design_and_interface.pdf ? audio_post-processing_interface_v1.13.pdf ? audio customization v1.0.pdf free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 47 audio block diagram audio block diagram " 6 @ . 0 6 5 - " 6 @ . 0 6 5 3 " 6 @ 0 6 5 @ 1 " 6 @ 0 6 5 @ / " 6 @ ' . * / - " 6 @ ' . * / 3 . 6 9 . 6 9 4 u f s f p u p . p o p ' . " . s b e j p d i j q 7 p j d f 4 j h o b m " v e j p 4 j h o b m 7 p j d f " n q " v e j p " n q 3 " v e j p " n q - " 6 @ 7 * / @ 1 " 6 @ 7 * / @ / " 6 @ 7 * / @ / " 6 @ 7 * / @ 1 . 6 9 7 p j d f 4 j h o b m " v e j p - $ ) % " $ " v e j p 3 $ ) % " $ 7 p j d f % " $ 7 p j d f " % $ 1 ( " audio buffer voice buffer microphone pga free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 48 audio buffer gain audio buffer gain ? analog gain setting ? loudspk mode ? audio buffer ? 112= -1db ?positive gain results distortion ? external amplifier ?increasing external amplif ier gain for louder volume ? earphone mode ? audio buffer ? 112= -1db ?positive gain results distortion ? external rc trade-off w p j d f # v g g f s < e # > b v e j p # v g g f s < e # > t f u u j o h j o f o h j o f f s j o h n p e f free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 49 external rc value external rc value ? rc value on mp3_out path 1) bandwidth: 2) amplitude degradation: 3) larger resistance, better bass , smaller volume ; 4) larger capacitance, better bass , higher cost, larger pcb area . 5) pout < earphone speaker rated power 6) example: ? (r1, c, fc, amplitude) ? ( 100ohm, 47uf, 25.65hz, -12.3db) rc f c 2 1 = 2 1 2 log 20 ] [ r r r db amplitude + = + c 47u (4v) + c 47u (4v) 150 r1 hp jack 1 2 3 150 r1 agnd mp3_outr mp3_outl r1 c r2 r=r1+r2 2 ) ( 2 r v p rms out = free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 50 external rc value external rc value ? different types of capacitor s have different distortion. ? distortion: tantalum cap. > mlcc x5r > mlcc y5v ? don?t use mlcc y5v in audio path/ mic0/ fm_in ? capacitors? thd+n vs. freque ncy are showed as below: ? green: x5r (+/-10%); audio p recision analyzer rin=100kohm ? red: x5r (+/-10%); audio precision analyzer rin=100kphm ? blue: y5v (+80%, -20%); audi o precision analyzer rin=300ohm ? cyan: y5v (+80%, -20%); a udio precision analyzer rin=300ohm mediatek 02/21/08 21:55:08 external source thd+n vs frequency cap_thd+nvsfreq.at27 color sweep trace line style thick data axi s comment 1 1 blue solid 3 dsp anlr.thd+n ratio a left 6238evb (200mvrms, aa=10 0 2 1 cyan solid 3 dsp anlr.thd+n ratio a left 6238evb (200mvrms, aa=30 0 5 1 green solid 3 dsp anlr.thd+n ratio a left 6235evb (200mvrms, aa=10 0 7 1 red solid 3 dsp anlr.thd+n ratio a left 6235evb (200mvrms, aa=30 0 -120 +0 -100 -80 -60 -40 -20 d b 20 20k 50 100 200 500 1k 2k 5k 10k hz free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 51 external rc value external rc value ? tantalum capacitor ? can?t be operated under reverse bias, ? hp eint can?t be on earphone path. ? permissible reverse voltage: ? the reason of damage by reverse voltage ? reverse voltage will damage ta2o5, ? after ta2o5 is broken, there is large current passed through tantalum capacitor. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 52 external rc value external rc value ? hp eint suggestion ? 18-pin i/o ? an extra pin for hp eint and accessory need a pull-low resister. ? 6-pin earphone jack ? two extra pull-low resistors on ch-l/r b301 blm18bd252sn1 0603 b300 blm18bd252sn1 0603 b302 blm18bd252sn1 0603 c325 tctp0j476m8r-y2 cap-0805 vr315 0402 vr314 0402 vr316 0402 c326 1nf 0402 eint7_headset 2 fm_ant 14 c327 1nf 0402 c329 1nf 0402 c330 2.2uf 0402 r381 4.7k 0402 r308 100 0402 mp3_outr 2,3 c324 33pf 0402 mp3_outl 2,3 c328 33pf 0402 r312 100 0402 vr317 0402 c323 100pf 0402 au_moutr 2,3 au_moutl 2,3 mp3_outl 2,3 mp3_er r314 1k 0402 mp3_outr 2,3 l306 blm18bd252sn1 0603 mic_hp r380 4.7k 0402 vr318 0402 j302 earphone phonejack(ajr4r-6kxxx1) gnd 1 mic 2 outr 3 outl 4 na 5 na 6 c322 tctp0j476m8r-y2 cap-0805 eint7_headset: h= earphone plug in l= earphone plug out free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 53 crosstalk= 70db crosstalk= 45db audio traces audio traces ? crosstalk issue ? avoid ch-l and ch-r?s signal interfering to each other ? (1) pcb layout ? protected audio r & l stereo trace by gnd separately. in headset mode, please separate l/r channel and microphone trace by gnd. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 54 audio traces audio traces ? crosstalk issue ? (2) earphone accessory: ? separated gnd of ch-l and ch-r. ? connect the gnd of ch-l and ch-r at the end of earphone jack. not connect the gnd at earphone microphone. ? (3) the bead at fm ant on earphone path may degrade crosstalk about 15db. ? choose bead with low drc bead and good thd+n ? it is a trade-off between fm feature and crosstalk performance. mic+ mic+ hp hp l r x o free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 55 i/o connector (10pins) i/o connector (10pins) ? uart + usb + earphone tp901 fm_ant 7 t911 esd9x5.0st5g t910 esd9x5.0st5g t909 esd9x5.0st5g utxd1 1 xmp3_l 3 xmp3_r 3 l903blm18bd252sn1 l902blm18bd252sn1 l904blm18bd252sn1 c904 1n l901 blm18bd252sn1-(0603) d903 sdm20u40-7/rb520s-30 1 2 r916 47k vdd c903 1n xmic 3 v t907 m1005c080mtaab j903 mini 10pin i/o a txd 1 vchg+ 2 rxd 3 d- 4 gnd_fm 5 d+ 6 mp3_l 7 mic 8 mp3_r 9 accdet 10 gnd3 14 gnd2 11 gnd0 12 gnd1 13 urxd1 1 usb_dm 1 vchg/usb_pwr r318 1k headset detection eint0_acc_det 1 usb_dp 1 c907 33p v tn904 avsc18s05e007 c908 33p c906 33p tp905 tp906 c905 1n free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 56 case study (1) case study (1) ? audio pop noise ? loudspk mode ? tuning external audio amplifier on/off delay time ? mp3_outl/r to external amplifier input must add coupling capacitor to avoid voltage drop. ? earphone mode ? turn on de-pop function by software ? tantalum capacitor +/- reverse mounting. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 57 case study (2) case study (2) ? loudness without distortion ? loudspk mode ? audio buffer gain <112 ? increase external audio amplifier gain ? earphone mode ? audio buffer gain <112 ? decrease resistan ce on earphone path ? increase capacitanc e for good bandwidth ? microphone pga ? uplink speech volume ? nvram_default_audio.c: #define gain_nor_mic_vol3 ? engineering mode: audio, norm al mode. microphone, volume3 ? sound recorder/video recording volume ? nvram_default_audio.c: #define gain_nor_mic_vol4 ? engineering mode: audio, norm al mode. microphone, volume4 ? fm recorded file playback ? increase fm_record_pga if fm playback volume is small. ? mcu\1audio\afe2.c: #defi ne fm_radio_recording_volume free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. MT6516 design notice (speech) MT6516 design notice (speech) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 59 new proposed microphone circuit new proposed microphone circuit ? advantage ? 10uf capacitor is not needed any more ? less passive components are needed ? circuit: normal mode c306 33pf c305 33pf micn0 2 c310 100nf 0402 c300 100nf 0402 mic+ l300 2000@1ghz r300 2k 0402 r302 2k 0402 micp0 2 vr300 0402 au_micbias_p 2 mic300 mic mic/od4/id1 1 2 r301 10k free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 60 new proposed microphone circuit new proposed microphone circuit ? circuit: headset mode au_micbias_p c318 100nf 0402 r303 2k 0402 micn1 2 micp1 2 c311 100pf 0402 c314 100nf 0402 r317 10k 0402 c321 33pf 0402 r306 2k 0402 headset gnd c332 33pf 0402 r318 1k 0402 mic_hp auxadin5 2 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 61 new proposed microphone circuit new proposed microphone circuit ? layout consideration-normal mode c306 33pf c305 33pf micn0 2 c310 100nf 0402 c300 100nf 0402 mic+ l300 2000@1ghz r300 2k 0402 r302 2k 0402 micp0 2 vr300 0402 au_micbias_p 2 mic300 mic mic/od4/id1 1 2 r301 10k should be routed in differential should be routed in differential connect the 4 gnd together and then connect to the main gnd by a single via rload vr free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 62 new proposed microphone circuit new proposed microphone circuit ? layout consideration-headset mode au_micbias_p c318 100nf 0402 r303 2k 0402 micn1 2 micp1 2 c311 100pf 0402 c314 100nf 0402 r317 10k 0402 c321 33pf 0402 r306 2k 0402 headset gnd c332 33pf 0402 r318 1k 0402 mic_hp auxadin5 2 connect the 4 gnd together and then connect to the main gnd by a single via should be routed in differential should be routed in differential free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 63 how to optimized how to optimized rload rload ? the rload can be calculated by the follow procedure ? measure the voltage on the microphone mic_p in a quite environment ? select a rload to let vr has almost the same voltage as mic_p free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. mt mt 6516 camera design notice 6516 camera design notice free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 65 camera design note camera design note ? ? parallel interface parallel interface ? all camera pins are dedicated ? layout notice ? cmmclk, cmpclk need to be well shielded by gnd plane ? bb side power level ? vdd33_camera (aj9, ak10) = camera side io level dovdd vcam_d r2 4.7k scl sda cmdat9 cmdat0 cmdat8 cmdat7 cmdat5 cmdat4 cmdat3 cmdat2 cmdat1 cmdat6 cmrst cmstrobe cmhref cmvref cmpdn j1 hirose fx12b-40p-0.4sv avdd 1 dvdd 2 dovdd 3 dgnd 4 agnd 5 strobe 6 siod 7 sioc 8 resetb 9 vsync 10 hsync 11 pwdn 12 mclk 13 pclk 14 data9 15 data8 16 data7 17 data6 18 data5 19 data4 20 data3 21 data2 22 data1 23 data0 24 dgnd 25 dgnd 26 mdp1 27 mdn1 28 dgnd 29 mcp 30 mcn 31 dgnd 32 mdp0 33 mdn0 34 dgnd 35 r1 4.7k rcp rdn0 rdp0 rcn rdn1 rdp1 cmpclk vcam_d vcam_a j2 + 1 + 2 + 3 cmmclk vcam_a sioc ag5 scl1 resetb aj7 cmrst data0 ~ data9 av2,al9,at4,am8,au3 an7,an5,ak8,ap4,al7 cmdat0~cmdat9 strobe an3 cam_strobe pwdn siod mclk pclk hsync vsync camera side am4 cmpdn ap2 sda1 ar3 cmmclk ag9 cmpclk at2 cmhref ah8 cmvref MT6516 (pin definition) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 66 camera design note camera design note ? ? mipi (csi mipi (csi - - 2) interface 2) interface pwdn am4 cmpdn cam_strobe strobe an3 resetb aj7 cmrst mdn0 mdp0 mcn mcp mdn1 mdp1 camera side e1 rdn0 e3 rdp0 f2 rcn g3 rcp g1 rdn1 h2 rdp1 MT6516 (pin definition) vcam_d r2 4.7k scl sda cmdat9 cmdat0 cmdat8 cmdat7 cmdat5 cmdat4 cmdat3 cmdat2 cmdat1 cmdat6 cmrst cmstrobe cmhref cmvref cmpdn j1 hirose fx12b-40p-0.4sv avdd 1 dvdd 2 dovdd 3 dgnd 4 agnd 5 strobe 6 siod 7 sioc 8 resetb 9 vsync 10 hsync 11 pwdn 12 mclk 13 pclk 14 data9 15 data8 16 data7 17 data6 18 data5 19 data4 20 data3 21 data2 22 data1 23 data0 24 dgnd 25 dgnd 26 mdp1 27 mdn1 28 dgnd 29 mcp 30 mcn 31 dgnd 32 mdp0 33 mdn0 34 dgnd 35 r1 4.7k rcp rdn0 rdp0 rcn rdn1 rdp1 cmpclk vcam_d vcam_a j2 + 1 + 2 + 3 cmmclk vcam_a ? all mipi dsi pins are dedicated that connect from bb to lcm ? 1 clk lane + 2 data lanes ? bb side tvrt (pin g5) connect 1.8k 1% resistor to gnd and close to bb ? layout notice ? all signal pairs need to 50ohm impedance matching for single end and 100ohm for differential ? all signal length need be equal a nd well shielded by gnd plane ? bb side power level ? vdd33_camera (aj9, ak10) = camera side io level dovdd ? dvdd12_mipi (j7, k8) connect to vcore(1.2v) ? dvdd28_mipitx (h8, j9), dvdd28_mipirx(j5), avdd28_mipitx (g7) , and vdd33_mipi (l11) connect to vdd (2.8v) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. mt mt 6516 6516 lcm lcm design notice design notice free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 68 display interfaces display interfaces ? various interface support ? 8080 host if (mipi dbi) ? 8/9/16/32-bit serial if ? rgb interface (mipi dpi) ? mipi dsi interface ? high performance lcd controller enable wide range of display resolution ? landscape or portrait mode. ? from 128x96(subqcif) ~ 852x480(wvga) ? advance color processing ? embedded lcd gamma correction table. ? color correction matrix. ? true color support. ? contrast, brightness adjustment. ? 6 overlay layers with per-pix el alpha channel and gamma table ? 2x or 4x temporal dithering free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 69 lcm design note lcm design note ? ? cpu (host) interface cpu (host) interface ? lcm side must have fmark(f_ sync) frame update hw pin and need to connect to lpte(w3) for tearing free tier-1 performance ? lcm side iovcc reserve vmem(1.8v) & vdd(2.8v) option for 1.8v nand application ? bb side power level ? vdd33_nld (pin aa9, ac9, w9) = lcm side iovcc level fmark / f_sync w3 lpte d17~d0 /reset /rd rs /wr /cs lcm side aa5, af2, ap6, ae3, ab8, ad4, ac7, aj1, ah2, al1, ag3, af4, ac5, ak2, ad6, aj3, ad8, an1 nld17~nld0 w7 lrstb y2 lrdb y4 lpa0 aa1 lwrb w1 lpce0b MT6516 (pin definition) j500 lcd-44pin-con iovcc 1 vci 2 gnd1 3 led6a 4 led5a 5 led4a 6 led3a 7 led2a 8 led1a 9 gnd2 10 lcm_id 11 /cs 12 /wr 13 rs 14 /rd 15 /reset 16 d17 17 d16 18 d15 19 d14 20 d13 21 d12 22 d11 23 d10 24 d9 25 d8 26 d7 27 d6 28 d5 29 d4 30 d3 31 d2 32 d1 33 d0 34 blc 38 xl 40 yd 41 xr 42 yu 43 gnd3 39 gnd4 44 fmark 37 im3 35 im0 36 led_ca4 led_ca3 led_ca2 led_ca1 led_ca6 led_ca5 r505 0 1 2 3 lrstb lpce0b_main_lcm lwrb lpa0 lrdb vr501 c501 2.2u nld1 nld10 nld9 nld8 nld2 tp_y- tp_x- nld0 nld7 nld11 tp_y+ tp_x+ nld4 nld6 nld5 nld13 nld3 nld12 nld15 nld14 nld16 nld17 adc2_lcmid r513 0 c500 2.2u vr500 lpte r504 nc gpio29_main_lcm_blc vmem vdd free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 70 lcm design note lcm design note ? ? rgb (dpi) interface rgb (dpi) interface ? rgb (dpi) interface s eparated into two groups ? 3 wire (or 4 wire) spi interfac e for lcm initial code setting ? image databus (dedicated pins and co nnect from bb to lcm directly) ? layout notice ? dpick, lsck must well isolated by gnd plane ? all image signal length need to be equal as best. ? bb side power level ? vdd33_nld (pin aa9, ac9, w9) = lcm side iovcc(vddi) level rst w7 lrstb dck ac1 dpick b0 ~ b5 al1,ah2,aj1,ac7,ad4,ab8 nld8 ~ nld13 g0 ~ g5 ae3,ab6,af2,aa5,ag1,y8 nld14 ~ nld19 r0 ~ r5 denb hsync vsync spi_clk spi_sdi spi_cs lcm side ab2 dpide ac3,aa7,ad2,ae1,ab4,y6 nld20 ~ nld25 w5 dpihsync aa3 dpivsync u5 lsck u1 lsda v4 lsce0b MT6516 (pin definition) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 71 lcm design note lcm design note ? ? mipi (dsi) interface mipi (dsi) interface ? all mipi dsi pins are dedicated that connect from bb to lcm ? 1 clk lane + 2 data lanes ? f_sync for mipi dsi command mode connect to dedicated pin lpte ? bb side tvrt (pin g5) connect 1.8k 1% resistor to gnd and close to bb ? layout notice ? all signal pairs need to 50ohm impedance matching for single end and 100ohm for differential ? all signal length need be equal and well shielded by gnd plane ? bb side power level ? vdd33_nld (pin aa9, ac9, w9 ) = lcm side iovcc(vddi) level ? dvdd12_mipi (j7, k8) connect to vcore(1.2v) ? dvdd28_mipitx (h8, j9), dvdd28_mipirx(j5), avdd28_mi pitx (g7), and vdd33_mipi (l11) connect to vdd (2.8v) f_sync / te w3 lpte tdn1 b4 pad_tdn1 tcp b2 pad_tcp tcn c3 pad_tcn reset tdp1 tdn0 tdp0 lcm side a3 pad_tdp1 w7 lrstb d2 pad_tdn0 c1 pad_tdp0 MT6516 (pin definition) vci_lcm leda ledk j1 gnd 1 datap0 2 datan0 3 gnd 4 datap1 5 datan1 6 gnd 7 clkp 8 clkn 9 gnd 10 vci 11 reset 12 gnd 13 leda 14 ledk 15 gnd 17 f_sync 16 tdn1 tdp0 tdn0 tdp1 lpte tcp tcn lcm_rst free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. high speed high speed m m emory emory l l ayout ayout rule rule mobile ddr sdram mobile ddr sdram free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 73 outline outline ? overview ? high speed memory layout considerations ?placement ? suggested routing order ? ground/power plane ? signal layout ? other general layout considerations ? check list free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 74 overview overview ddr sdram signals ? we can categorize ddr sdram interfaces into 4 groups as follows. ? signal quality could be degraded by any pcb layout issue. ? we must take care of diff erent groups of ddr sdram. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 75 high speed memory layout considerations high speed memory layout considerations ? it is recommended that the pcb layout of memory interface is the first priority for your design. ? we can check memory pcb layout characteristics in the following order: 1. placement 2. suggested routing order 3. ground/power plane 4. signal layout 5. other general layout considerations free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 76 ? placement ? memory device must place as close to bb chip as possible ? avoiding extra long trace (max trace1500mil) ? avoiding other high frequency de vices place close to memory ? route these traces smoothly, reduce the via counts and avoiding traces interlace if possible ? you can swap byte in order to reduce trace s interlace if there has restriction in placement (only for sd/ddr ram) ? ?swap byte? means to connect dqs0 from bb chip to memory dqs1 in order to reduce the interlacing of data traces, e.g. d[0:7] from bb chip to memory d[8:15]. ? note: swap the corresponding dqs ,d qm and dqx at the same time. byte0 byte0 byte1 byte1 byte1 byte0 byte0 byte1 swap high speed memory layout considerations high speed memory layout considerations free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 77 high speed memory layout considerations high speed memory layout considerations ? layout routing ? please route traces by the following order: 1. power/gnd plane 2. data group 3. clock group 4. command/address/control groups ? because high frequency signal integrity is highly related to solid ground and power plane, data groups are operating at twice the clock frequency. ? it is recommended that the designer takes care of the layout routing in the very beginning of the design. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 78 bb memory traces power plane (vmem) vmem power trace bypass cap of vmem should be connected to the power plane. high speed memory layout considerations high speed memory layout considerations ? ground/power plane ? a solid power/ground plane must be prov ided near all traces routing layers. ? it will minimize the ground return current to get better performance. ? there are 2 methods for reference: 1. it is recommended all traces are routed above a solid gnd plane , and there is a power plane (memory power domain) und er the gnd plane if possible. e.g. 1st layer : traces 2 nd /3 rd layer: trace (strongly recommended - the same group of traces routed on the same layer ) 4rd layer: gnd 5th layer: power plane (vmem) if possible, which is under the traces of memory interface. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 79 high speed memory layout considerations high speed memory layout considerations 2. all traces are routed above a solid gnd plane , and under a dc power plane (vbat domain) to provide good shield (the traces of memory interface protected by vbat and gnd) e.g. 1st layer : vbat 2nd layer: trace (strongly recommended - the same group of traces routed on the same layer) 3rd layer: trace 4th layer: gnd note: all power trace bypass capacitors must be placed as close to the devices' power pins as possible, and all capacitor's gnd should have the shortest and widest trace to the gnd plane. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 80 ? layer definition ? m - ge ?< ?c[ ? stack-up suggested layer definition suggested layer definition signal (horizontal) l6 signal (vertical) l5 power l4 gnd l3 signal (horizontal) l2 signal (vertical) l1 6 layer for evb l1 l2 l3 l4 l5 l6 pp (3mil) signal pp (3mil) signal core ( @ i ? ) gnd pp (3mil) power signal pp (3mil) signal (x) (0) d core y? , ?-5i4 4y pp ? pp ? ,l1 ? l2 y signal t e ?y return path pp ? ,l5 ? l6 y signal t e ?y return path free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 81 high speed memory layout considerations high speed memory layout considerations ? if we take a good power plane under traces, we can get good power trace impedance performance. no power plane no power plane there are a power plane under memory there are a power plane under memory interface traces interface traces the impedance reduce to half the impedance reduce to half when added power plane when added power plane free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 82 high speed memory layout considerations high speed memory layout considerations data jitter=1.04ns strobe jitter=85.6ps p-p= 499mv data jitter=1.22ns strobe jitter=145ps p-p= 598mv data jitter=0.892ns strobe jitter=78.5ps p-p= 307mv only power trace only power trace not good added a small added a small power plane power plane under bb chip under bb chip better added power added power plane under bb plane under bb chip and dram chip and dram best data jitter=1ns strobe jitter=348ps @output of receiver @io pad @io pad of receiver of receiver @io pad of driver @io pad of receiver @io pad of driver @io pad of driver @output of receiver @io pad of receiver @output of receiver data jitter=0.775ns strobe jitter=261ps data jitter=0.584ns strobe jitter=110ps add a power plane on pcb to enhanc e performance (reducing signal jitter) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 83 high speed memory layout considerations high speed memory layout considerations signal layout ? we categorized all signals into 4 groups, prioritized as follows: ? 1st priority: data group ? 2nd priority: clock group ? 3rd priority: control/command groups ? if possible, control trace impedance between bb chip and dram, trace impedance is related to pcb dielectric constant, trace width, trace thickness, and routing method (using microstrip or stripline). ? the performance will get better if signal trace impedance is under control. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 84 high speed memory layout considerations high speed memory layout considerations 1. data group (1/2) ? dqx and dqs must be routed in a gr oup and routed in the same layer and reduce via counts if possible. e.g. d[0:7] is aligned to dqs[0]; d[8:15] is aligned to dqs[1]. so, d[0:7] must be rout ed in a group with dqs[0], and d[8:15] must be routed in a group with dqs[1]. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 85 space width: 1.5w dqs1 trace width: w dqs0 trace width: w gnd via required on entire gnd shield high speed memory layout considerations high speed memory layout considerations 1. data group (2/2) (remind : power/ gnd plane is the most important) ? within the same data group: (m ax. trace length ? 500 mil )< trace length < (max. trace length) ? between different data group: (max. trace length ? 500 mil )< trace length < (max. trace length) | dqs - clock trace l ength | < 300 mil ? if possible, control data trace impedance to ensure it meets the requirement (please check input im pedance of memory). ? within the same group if dqx trace width is w, the space be tween dqx is 1.5 w. ? to reduce the crosstalk on dq sx , gnd shielding is required. ? if the trace width is w , the trace space between dqsx and g nd is at least 1.5w, and the width between dqs0 and dqs1 is at least 3w. ? do not route data group traces in parallel for a long distance. 12mil dqsx serpentine spacing serpentine spacing free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 86 space width 1.5w 1.5w 1.5w gnd need gnd via on whole gnd shield differential clock pair (trace width: w) high speed memory layout considerations high speed memory layout considerations 2. clock group (1/2) ? there are a differential pair of high speed clocks in the ddr sdram memory device, so we need to take care of t hese traces to ensure the clock integrity. ? route these 2 clock traces in para llel and keep equal trace length. ? control clock trace impedance (please check memory device ). if clock trace is w the space between clk and /clk is at least 1.5w and there need gnd shield wrap around the clock differential pair. the space gnd and clock trace at least 1.5w , and the gnd shield need enough gnd via if we c an not give enough gnd via , we would rather take gnd shield o ff , and the space to adjacent signals is at least 2w. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 87 high speed memory layout considerations high speed memory layout considerations 2. clock group (2/2) ? away from other high frequency traces ? each clock trace must have solid power and ground plane near the entire route. ? each clock trace is recommended to route on the same layer to reduce via number, and to keep the same trace characteristics. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 88 high speed memory layout considerations high speed memory layout considerations 3. control/command groups ? every trace must have soli d power and ground plane near the entire route. ? every trace is recommended to r oute on same layer to reduce via number, and to keep the same trace characteristics. ? route address traces from prio rity a0 (most toggled ) to a15 (less toggled), and a0 shoul d be close to ground if possible. |trace length - clock trace length| < 500 mil within cmd/adr group: |max. (cmd/adr trace length) ? min. (cmd/adr trace length)| <250 mil ? remind : power ground is the mo st important , you just need to meet the traces match criterion as possible ? if serpentine is needed , the spacing is at least 12mil free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 89 check list check list ? placement ? memory device must placed as cl ose to the bb chip as possible. ? avoid extra long trace (max. trac e: 1500 mil) and other high frequen cy devices placed close to memory ? route these traces smoothly, reduc e the via counts and avoiding traces interlacing if possible ? considerations on ground/power plane (power/gnd plane is the most important ) ? it is recommended all traces to be routed above a solid gnd plane, and there is a po wer plane (memory power domain) under gnd plane if possible. e.g. 1st layer: traces 2nd layer: trace (strongly recommended ? the same group of traces routed on the same layer) 3rd layer: gnd 4th layer: power plane (vmem) if possible, the plane is under the traces of memory interface. ? or all traces are routed above a solid gnd plane, and un der a dc power plane (vbat domain) to provide a good shield (the traces of memory interface protected by vbat and gnd). e.g. 1st layer : vbat 2nd layer: trace (strongly recommended ? the same group of traces routed on the same layer) 3rd layer: trace 4th layer: gnd ? trace length is as match as possi ble , all traces refer to clock , wi thin 500mil length difference is acceptable (ddr , dqs and dq is a group , and ddr clock ,/clock are within 100mil) ? if serpentine is needed , the spacing is at least 12mil 12mil dqsx serpentine spacing serpentine spacing free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. schematics and cable design MT6516 usb design notes MT6516 usb design notes free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 91 mtk usb2.0 solution introduction mtk usb2.0 solution introduction ? this document introduces mtk usb2.0 design and some points for attention. ? mtk usb2.0/ otg device can operate at usb2.0 high-speed (hs) mode (480mb/s) and full-speed (fs) mode (12mb/s). ? general hs eye diagram is shown as below. the output swing is differential 0.4v. bad eye diagram will lead to certification fail or signal integrity problem. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 92 usb pin definition usb pin definition ? usb2.0 pin out description. ? general pins ? optional pins for supporting otg * comparator used fo r detecting changes of vbus voltage. io pad_usb_vbus 1 analog 1.2v ground gnd avss12_usb 8 analog 1.2v supply. vdd avdd12_usb 7 analog 5.1k reference resistor io pad_usb_vrt 6 analog 3.3v ground gnd avss33_usb 5 analog 3.3v supply vdd avdd3_usb 4 usb serial differential bus (positive) io pad_usb_dp 3 usb serial differential bus (minus) io pad_usb_dm 2 description type symbol pin optional function for usb otg id pin for detecting slave plug in. io pad_usb_id 9 description type symbol pin free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 93 must be 5.1k ohm, 1% place close to ic reserve bead and bypass capacitor for usb 1.2, 3.3v power don?t have to connect vbus/id schematics design for usb2.0 device (2/2) schematics design for usb2.0 device (2/2) ? MT6516 (device only) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 94 schematics design for usb2.0 high speed schematics design for usb2.0 high speed ? beware of usb_vrt pin should keep away from noise source and high speed clock data like camera databus. ? reserve 0402 cap (nc) on dp/dm for esd protection and rise time/fall time tuning for usb-if compliance test. ? if want to get usb-if otg logo, should use micro-ab connector. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 95 d- data line vusb 15k ohm r1 usb side inside mtk usb 15k ohm r2 d+ data line 100k ohm r4 inside mtk usb standard charger side d+ data line vusb d- data line 100k ohm r4 non-standard charger side 100k ohm r4 d+ data line inside mtk usb vusb d- data line usb/ charger detection usb/ charger detection ? used for MT6516 and later on mt k ics (mt6268/MT6516/mt6253) ? when charger interrupt happens, turn on d- pull high 100k ohm resistor and check the polarity of d- ? if the d- is low, it is usb charger, otherwise it is a standard or a non- standard charger free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 96 vusb 15k ohm r2 standard charger side d- data line 1.5k ohm r3 inside mtk usb d+ data line vusb non-standard charger side inside mtk usb 15k ohm r2 d+ data line 1.5k ohm r3 d- data line usb/ charger detection (cont.) usb/ charger detection (cont.) ? then check whether it is standard or non-standard charger. turn on d+/d- internally 15k ohm pull low resistor and d+ 1.5k ohm pull high resistor at the same time. ? check d- polarity. if the d- is high, it is standard charger, otherwise it is a non-standard charger. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 97 high speed usb layout checklist (1/2) high speed usb layout checklist (1/2) ? general design and layout rules ? with minimum trace lengths, route clock source and hs usb differential pairs first. keep maximum possible distance between clocks/periodic signals to usb differential pairs to minimize crosstalk. ? route hs usb signal pairs toget her with equal length by using a minimum vias and corners. this reduces signal reflections and impedance changes. ? maintain parallelism between usb differential signals with the trace spacing needed to achieve 90 ohms differential impedance. ? when it becomes necessary to turn 90 , use two 45 turns or an arc instead of making a single 90 turn. this reduces reflections on the signal by minimizing impedance discontinuities. ? do not route usb traces under crystals, oscillators, clock synthesizers, magnetic devices or ics that use and/or duplicate clocks. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 98 high speed usb layout checklist (2/2) high speed usb layout checklist (2/2) ? general design and layout rules (conti.) ? stubs on hs usb signals should be avoided, as stubs will cause signal reflections and affect signal quality. ? avoid crossing over anti-etch if possible. crossing over anti-etch (plane splits) increases inductance and radiation levels by forcing a greater loop area. likewise, avoi d changing layers with high-speed traces as much as practical. ? keep hs usb signals away from high current area. the current transient during state transitions could induce noise to usb. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 99 avoid creating stubs if possible proper way to connect resistors or varistors d+ d- stubs stubs ? avoid creating unnecessary stubs on data lines, if a stub is unavoidable (for example: esd is sue), please keep the stub as short as possible. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 100 tp failure to maintain parallelism of usb2.0 data lines ground or power plane don?t cross plane splits avoid creating stubs proper routing technique maintains spacing guidelines poor routing techniques poor routing techniques ? cross a plane split. ? creating a stub with a test point. ? failure to maintain parallelism. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 101 case study (1/5) case study (1/5) ? case 1: ? 2a36/2a37 should be removed. large cap at usb_dp/usb_dm will lead to bad jitter performance. ? measured eye at board is shown below. it will occur turn-around error at system application. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 102 case study (2/5) case study (2/5) ? case 2: ? after bead, at least 0.1uf capacitor between vdd33_usb, vdd12_usb and ground must be added as follows. ? measured eye diagram has bad jitter performance. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 103 ? case 3: ? some time we got worse jitter due to poor layout, then vusb33 and vusb12 are coupled by noise. ? it is improved by increasing bypass capacitor c221 and c235. before modification improved after modification chip side case study (3/5) case study (3/5) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 104 original design without analog switch add different analog switch fairchild fsusb42 fairchild fsusb30 case study (4/5) case study (4/5) ? case 4: ? customer wants to share usb data pi ns with audio/uart pins through the same 5-wire usb connector by using analog switch. ? different analog switches cause different attenuation of signals; please make sure component and layout wi ll get proper eye diagram. ? no suggestion on using analog switch, 11-pin usb connector could be used instead. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 105 cable with large series resistance design with normal usb cable cable with proper series resistance case study (5/5) case study (5/5) ? case 5: ? sometimes customer may design a special connector for usb, such as 18-pin i/o. ? poor cable will cause poor performance. ? please follow usb cable design guide. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 106 conclusions conclusions ? layout and component selection are critical for usb2.0 high speed performance ? need to follow the design rule or there might be compatibility issue happens ? grounding and shielding are both critical when design usb2.0 high speed capable cables ? it can maintain usb signal quality with little jitter/ signal distortion caused by cable design ? please refer to ?mtk usb2.0/ otg design guide ? for more detail. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. mt6 mt6 516 516 factory mode & factory mode & engineer mode notice engineer mode notice copyright ? mediatek inc. all rights reserved. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 108 engineer mode and factory mode engineer mode and factory mode ? factory mode ? enter phone menu ? enter ? *#66*# ?, then dial ? engineer mode ? enter phone menu ? enter ? *#3646633# ?, then dial free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 109 factory mode menu tree factory mode menu tree free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 110 engineer mode menu tree engineer mode menu tree free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 111 flash tool flash tool download flow download flow ? bootloader download ? use uart1 to download bootloader ? windows mobile image download ? connect both uart1 and usb to download full winmo image ? flash tool can combine the two steps above. (must connect both uart1 and usb to pc first !) ? please refer to flash tool document in detail. download download bootloader bootloader download image download image free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 112 download tool download tool o? load f e y flash.bin MT6516_mldrnandformtk.nb0 MT6516_ebootnand.nb0 then press download all free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 113 meta meta link link (ap side) (ap side) ? install smartphone meta tool. ? how to enter meta mode ( uart1 ) ? if target have not been in meta mode, click ?reconnect? button, then connect phone; ? phone will power on and enter in to meta mode automatically ? uart can support up to 115200bps baud rate free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 114 meta meta link link (modem side) (modem side) ? install smartphone meta tool (for first time) ? link uart4 on handset to pc ? open hyper terminal on pc and set correct com port and parameters. ? press ? send key ? and ? end key ? to power on. ? set boot to meta mode: enter 9->3->1 ? enter 0->0, continue to boot to meta mode ? close hyper terminal, switch uart4 to uart1. (uart1 link to pc) ? wait about 12 seconds. ? execute meta tool ? choose uart and enable ? connect target already in meta mode ? in option menu. ? can backup/restore ca libration data in ? update parameter ? as feature phone. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. mt6 mt6 516 516 m m emory emory s s upport upport plan plan copyright ? mediatek inc. all rights reserved. mtk mvg (memory verification group) apr 2009 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 116 MT6516 platform (2g/1g) +1g (x32) nand + mobileddr mcp mcp mcp type samsung k522f1gacm-a060 (2g+1g, 1.8v* , bga137) ? w0919 elpida ehd013011ma-60 (2g+1g, 1.8v , bga137) ? w0921 toshiba tya000b801cflp40 (2g+1g, 1.8v , bga137) ? w0922 numonyx nandbar4n5bzbc5e (2g+1g, 1.8v , bga137) ? w0923 micron mt29c2g24maklaja-6 (2g+1g, 1.8v , bga137) ? w0924 hynix h8bcs0pj0mcp-56m (1g+1g, 1.8v , bga137) ? w0925 samsung k522h1gacd-a060 (2g+1g, 1.8v , bga137) ? w0926 micron mt29c1g24mavlaja-6 (1g+1g, 1.8v , bga137) ? w0927 micron mt29c1g24maclaja-6 (2g+1g, 1.8v , bga137) ? w0928 memory p/n (week available) nand(slc, 2k page) + 133/166mhz mobileddr edge smart phone segment edge smart phone edge smart phone * voltage supply of nand flash. ** for devices not included in th e weeks available, pl ease contact with mtk pm for status update. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. appendix appendix copyright ? mediatek inc. all rights reserved. peripherals design notice (gps/dtv) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. MT6516 MT6516 wifi/bt co wifi/bt co - - module application note module application note 2009/4 wcp/rp1/w.wei free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 119 outline outline z module function block and reference design ? module function block ? module reference design ? reference interface assignment ? key component list z schematic and layout design guide ? schematic design guide ? layout design guide free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 120 wi wi - - fi/bt fi/bt combo module product definition combo module product definition ? full-featured wi-fi 802.11b/g and bt 2.1 + edr combo module ? small-size package: 9.5 10.5 1.4 mm lga (< 10 10 mm) ? mtk?s proprietary superior wi-fi/bt co-existence performance ? wi-fi and bt co-existence shares the 26 mhz clock frequency. ? metal em interference shielding ? antenna: dual antenna (mandatory)/single antenna (optional) ? rohs complaint sample: sep. 2008 mp: 2009/02 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 121 mtk combo module block diagram mtk combo module block diagram sdio/spi interface gpio eeprom 1.8v 3.3v combo filter pcm interface uart interface bluetooth soc (mt6611 wlcsp) coexistence balun switch bpf pa wi-fi soc (mt5921p wlcsp) ref clock ant1 vbat tx/rx 32k sleep clock ant2 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 122 wi wi - - fi features fi features ? advanced wi-fi features ? 802.11b/g/e/i/h/k/w compatible ? ieee 802.11e qos (wmm/wmm-ps) ? background scan for specific ssid networks ? ieee 802.11i advanced secu rity (wep/tkip/aes/wpa/wpa2) ? 802.11e optional u-apsd, dls ? 802.11 power saving mode ? wakeup by specific pa cket (pattern search) ? thermo-sensor to resi st temperature change ? voice over wlan (vowlan) ? uma (unlicensed mobile access) technology ? voip over wlan ? software support ?win ce 5.0 ? win mobile v5.0/6.1 ? win mobile v7.0 (planning) ? linux v2.6 (planning) ? wi-fi certified free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 123 bluetooth features bluetooth features ? radio features ? fully compliant with bluetooth 2.1+edr ? low-if architecture with high performance linearity ? supports bluetooth class 2 and 3 ? tx transmit power: 4 dbm ? 90 dbm sensitivity with exce llent interference rejection performance ? 3.5 x 3.5 x 0.6 mm (m ax.), 0.5 mm pitch wlcsp ? baseband features ? up to 7 simultaneous active acl links ? supports 3 simultaneous sco and esco links sco and scatternet ? supports lower power mode (sniff, hold and park mode) ? ultra low power consumption in sleep mode ? supports afh and pta for wlan/bt coexistence ? software features ? supports standard hci interface ? supports more than 15 profiles in mediatek platform mt6611 function block free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 124 module share clock with daisy chain module share clock with daisy chain wifi power need to power on to keep daisy chain working normally. wifi can be shut down only as bt power off. 26mhz osc. mt5921+mt6611 module free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 125 co-module reference design j900 mm8130-2600b coaxial/con/mm8130-2600b 2 3 4 1 5 6 ame8801 sot-25-5 byp 4 vout 5 vin 1 gnd 2 en 3 r918 0r 0402 tcvcxo 26mhz y900 tcxo3225 e/d 1 gnd 2 o/p 3 vdd 4 r917 910r 0402 r912 0r 0402 r907 100k c900 2.2uf 0603 c911 2.2uf 0603 u901 co_module pavdd33 1 gnd 2 wlan_led 3 bt_gpio1 7 bt_clk 10 gnd 5 gnd 6 gnd 9 bt_vcc28out 8 gnd 4 bt_ldo28en 11 bt_vbat 12 bt_gpio4 13 gnd 14 wlan_ant 15 gnd 16 bt_pcmout 17 bt_pcmclk 18 bt_pcmin 19 bt_pcmsync 20 bt_urxd 21 bt_utxd 22 bt_gpio5 23 bt_gpio6 24 bt_32k 25 bt_gpio0 26 bt_sysrst_b 27 gnd 28 sd_d2 36 gnd 30 srclkena 31 vdd18 32 gnd 33 wlan_clk 34 sd_clk 37 osc_en 35 sd_d3 38 sd_d0 39 sd_cmd 40 sd_d1 41 int_n 42 ext_rst_n 43 wl_gpio2 44 dvddmio 45 dvdd33 47 bt_ant 29 dvdd28 48 gdn 49 wlan_32k 50 gnd 51 ant_sel_p 46 ant_sel_n 52 gnd 54 wl_gpio0 53 gnd 55 c902 4.7uf 0603 dvdd28 vdd18 +2.8v vwifi_3v3 vbt pavdd33 vdd18 dvdd28 r908 100k pavdd33 vwifi_3v3 bt_2v8 vwifi_3.0 vbat sdio_d2 2,5 sdio_clk 2,5 sdio_cmd 2,5 ext_rst_n sdio_d3 2,5 gpio116 2 bt_pcmin 2 bt_sysrst_b bt_32k bt_pcmclk 2 sdio_d0 2,5 bt_pcmout 2 osc_en bt_pcmsync 2 eint1 2 urxd3 2 utxd3 2 r926 100k daiclk 2 bt_pcmout 2 bt_pcmin 2 daipcmin 2 daipcmout 2 bt_pcmsync 2 bt_pcmclk 2 daisync 2 ext_rst_n gpio122 2 int_n 2 gpio115 2 int_n 2 bt_gpio0 2 eint5 2 bt_gpio0 2 sdio_d2 2,5 sdio_clk 2,5 sdio_cmd 2,5 sdio_d0 2,5 sdio_d3 2,5 bt_sysrst_b bt_32k sdio_d1 2,5 mc1da0 2,5 mc1cm0 2,5 mc1da1 2,5 mc1da2 2,5 mc1ck 2,5 mc1da3 2,5 wlan_32k sdio_d1 2,5 wlan_32k gpio123 2 bt_gpio1 btldo28en 2 btldo28en 2 gpio133_wifi_en 2 gpio132 2 bt_gpio1 rts input power c900 close to pin8 bt+wlan module osc_en host uart cts pin connect to gnd dvdd28 r910 nc 0402 srcklena c914 1uf 0402 r905 100k ant_sel_n ant_sel_n bt_clk ant_sel_p bt_clk ant_sel_p wlan_clk wlan_clk c901 1uf 0402 r901 100k 0402 r923 0 0402 c906 nc 0402 l900 nc 0402 r914 0r 0402 c912 1nf 0402 c903 1.2pf 0402 j901 mm8130-2600b coaxial/con/mm8130-2600b 2 3 4 1 5 6 tp902 tp30mil r903 0r 0402 ant901 wifi_ant ant901 copyright ? mediatek inc. all rights reserved. 126 interface assignment 26mhz oscillator list y900 - fk2600008 (load 15pf, 2.8v~3.3v) y900 epson sg-310scn. (load 15pf, 2.8v~3.3v) y900 txc 8w26000011 (load 15pf, 2.8v~3.3v) y900 aker sma026000-3dr3t0 (load 15pf, 2.8v~3.3v) 26mhz oscillator designator vendor part number item type pin function gpio133 wifi_rstb gpio116 wlan_32k mc1cm0 mc1da0 mc1da1 mc1da2 mc1da3 mc1ck i/o * ' sdio int5 wifi_interrupt i/o type pin function gpio122 bt_rstb gpio115 bt_32k utxd3 urxd3 daiclk daipcmout daipcmin daisync i/o * ' pcm uart int1 bt_interrupt i/o mt6611 pcm/uart power do main support 2.8~3.3v, not support 1.8v free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 127 wifi interface selection spi 1 0 0 0 0 0 sdio ant_sel_p trsw_n trsw_n 40mhz 26mhz 0 1 0 1 0 0 0 0 0 20mhz osc_freq0 ant_sel_p wlan_act main clock frequency selection fixed free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 128 schematic design guide(1)_power supply schematic design guide(1)_power supply z pavdd33 is a dedicated input pin for module internal pa power supply and please c onnect it to 3.3v. z dvdd28, dvdd33 and dvddmio are the wifi portion digital io power sourc e, please connected to 3.0v for optimum tx performance. z vdd18 is the wifi rf/analog/digital ldo input pin and can be connect ed to dc/dc 1.8v power source without degrading the module performance. bt_vcc28out dvdd28 vdd18 wifi/bt module pavdd33 1 gnd 2 wlan_led 3 bt_gpio1 7 bt_clk 10 gnd 5 gnd 6 gnd 9 bt_vcc28out 8 gnd 4 sd_d2 36 vdd18 32 gnd 33 wlan_clk 34 sd_clk 37 osc_en 35 sd_d3 38 sd_d0 39 sd_cmd 40 sd_d1 41 int_n 42 ext_rst_n 43 wl_gpio2 44 dvddmio 45 dvdd33 47 dvdd28 48 gdn 49 wlan_32k 50 gnd 51 ant_sel_p 46 ant_sel_n 52 gnd 54 wl_gpio0 53 pavdd33 dvdd33 dvddmio free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 129 bt power domain (2) bt power domain (2) ? distributed into two domains: v_bat and 2.8v ? v_bat power source could come from phone battery and bt_vcc28 is the internal ldo output pin. ? the bt 2.8v internal ldo was controlled by btldo28en pin connected to host gpio. btldo28en 2.2uf bt_vcc28out v_bat 4.7uf wifi+bt module bt_gpio1 7 bt_clk 10 gnd 5 gnd 6 gnd 9 bt_vcc28out 8 bt_ldo28en 11 bt_vbat 12 bt_gpio4 13 gnd 14 wlan_ant 15 gnd 16 bt_pcmout 17 bt_pcmclk 18 bt_pcmin 19 bt_pcmsync 20 bt_urxd 21 bt_utxd 22 bt_gpio5 23 bt_gpio6 24 bt_32k 25 bt_gpio0 26 bt_sysrst_b 27 gnd 28 sd_d2 36 gnd 30 srclkena 31 vdd18 32 gnd 33 wlan_clk 34 sd_clk 37 osc_en 35 bt_ant 29 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 130 schematic design guide(3)_clock source schematic design guide(3)_clock source z the wifi/bt device can share a same clock with a dais y chain function .this mec hanism allows bluetooth can work normally without extra power consumption even wifi operating in t he sleep mode. z the oscillator with 2.8~3.3v op erated voltage , 20ppm tol erance and 15pf load c apacitance is recommended 32khz clock for device sleep mode - the 32khz sourc e come from bb gpio output.. wlan_32k bt_32k bt_32k 25 wlan_32k 50 (gpio115) (gpio116) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 131 schematic design guide(4)_interface schematic design guide(4)_interface z please add 100k pull resistor s for the sdio data pi n except sd_clk pin. z for bt uart interface, pleas e note to connect the MT6516 host uart cts pin to gnd. wifi sdio interface bt uart interface free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 132 mt5921 power sequence mt5921 power sequence in order to prevent from the io dr iving unpredictable signals, it is recommended that the 1.8v is applied before io power or they are applied at the same time. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 133 ? the power on reset time is related to the frequency of main reference clock source. the normal functions are not ready until the power-on-reset was done. mt5921 power on /reset timing mt5921 power on /reset timing free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 134 mt6611 power on initialization mt6611 power on initialization ? hardware reset sequence & timing requirement ? (1) set bt_ldo_en to high ? (2) wait for at least 2ms ? (3) set bt_reset to high ? (4) wait for at least 1000ms ? (5) mt6611 is ready for receive hci command bt_ldo_en bt_reset (1) (2) (4) (5) (3) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 135 module layout guide ? 1/4 layer1 z please place the bypass capacitors to the 3.3/2.8/1.8v power rail as close as possible. z please keep 50 ohm transmission for the wifi/bt rf trace. z please isolate the wifi/bt main clock trace with gnd z please reserve the 9 square gnd pad for better performance for module bt_ant :50ohm trace wlan_clk free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 136 reference layout ? 2/4 layer2 layer1 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 137 reference layout ? 3/4 layer4 layer3 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 138 reference layout ? 4/4 layer6 layer5 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 139 module footprint layout guide module footprint layout guide pin1 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 140 module smt reflow profile module smt reflow profile free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. mt3326 application design note mt3326 application design note 2009 / 04 2009 / 04 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 142 ? mtk gps overview ? mt3326 gps feature ? mt3326 system block ? mtk gps reference design ? mt3326 schematic design note ? mt3326 pcb design note ? mt3326 qvl ? mt3326 debug sop ? mt3326 ate tool ? mtk gps tier one performance ? summary ? q&a agenda agenda free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 143 mt3326 features mt3326 features ? dimensions : ? 48-pin qfn lead-free pack age (6 x 6 x 0.85 mm) ? specification : ? host-based gps receiver ? 22 tracking/66 acquisiti on channel gps receiver ? supports waas/egnos/msas/gagan ? supports up to 210 prn channels ? jammer detecti on and reduction ? indoor/outdoor multi-pa th detection and compensation ? supports a-gps with fcc e911 compliance ? maximum fix update rate up to 10 hz ? reference clock support : ? tcxo frequency : 12 .6 mhz ~ 40.0 mhz ? interfaces : ? 2 uarts , spi , i 2 c , gpio ? low power consumption : ? acquisition mode : 39 ma ? tracking mode : 26 ma mt3326 compact layout area : 12 x 12 mm free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 144 mt3326 functional blocks mt3326 functional blocks ? gpio pull low ? gps receiver off ? gpio pull high ? gps receiver on saw tcxo ldo 2v8 external lna mtk gps ic mt3326 gps_pwr_en 29_rx0 26_tx0 22_sync uart2_tx uart2_rx bpi _bus6 (optional) MT6516 passive antenna 0.5 ppm optional: if 2.8v voltage can be provide by pmic, the external ldo can be eliminated. gpio mt6326 mt6326 pmic 2.8 v free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. mtk gps reference design mtk gps reference design free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 146 mtk gps total solution mtk gps sw build in mtk gps sw build in gps antenna review gps antenna review factory tool support factory tool support tier tier - - 1 field trial 1 field trial mtk gps phone total solution mtk gps phone total solution reference design reference design ch1 s22 log 5 db/ ref 0 db center 1 . 575 000 000 ghz span . 200 000 000 ghz cor avg 10 hld prm marker 1 1.57542 ghz 17 may 2000 13:18:10 1 2 3 4 1 : -29 . 366 db 1 . 575 420 000 ghz ch1 markers bw : . 019597108 ghz cent : 1 . 576044505 ghz q : 80 . 422 1_ loss : -29 . 366 db ch1 s22 1 u fs center 1 . 575 000 000 ghz span . 200 000 000 ghz cor avg 10 hld prm marker 1 1.57542 ghz 17 may 2000 13:18:39 1 2 3 4 1: 53 .414 -824 . 22 m 122 . 57 pf 1 . 575 420 000 ghz ch1 markers 2: 54 .098 -304 . 69 m 1 . 57604 ghz 3: 95 .941 -4 . 6016 1 . 56624 ghz 4: 40 .080 -28 . 146 1 . 58584 ghz free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 147 mt3326 reference circuit mt3326 reference circuit gps rf front end tcxo uart ldo c o m p a c t b o m a n d l a y o u t a r e a ! free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 148 mt3326 reference circuit (2/4) mt3326 reference circuit (2/4) gps rf front end lna input matching : please place these components close to lna input decoupling capacitor for noise filtering mixer input matching : please place these components close to mt3326_pin 46 antenna matching passive antenna : circular polarization patch antenna is recommend saw filter : for filtering jamming free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 149 mt3326 reference circuit (3/4) mt3326 reference circuit (3/4) frequency :16.368 mhz frequency stability : +/- 0.5ppm c1011 10nf c1013 1uf r1001 0r u1007 rakon/it3205be/16.368mhz vcc 4 out 3 gnd 2 nc 1 2v8 2v8 tcxo c1018 1uf (x5r) u1005 xc6221a182nr vin 4 ce 1 vss 2 vout 3 c1017 1uf r1002 100k 2v8 vbat gp019_gps_pwr_en 2 power tcxo ldo tcxo vcc : avoid the noise interference for frequency stability reserve 0 ohm to isolate the impact of pcb gnd temperature variation on tcxo. gpio from MT6516 to control ldo on/ off stabilize the ldo output voltage free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 150 mt3326 reference circuit (4/4) mt3326 reference circuit (4/4) gps_uart0 connect to mt6515 uart interface mt3326 supply voltage : *analog voltage : rf_1v5 * digital voltage : core_1v2 ldo i/o p capacitor : place these capacitors close to the mt3326 ldo input pin and output pin for stabilizing voltage optional : connect to MT6516 bpi_bus. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 151 pcb design flow pcb design flow placement placement layout 1: layout 1: rf trace rf trace layout 2 : layout 2 : tcxo tcxo --- --- clock trace clock trace layout 3: layout 3: ldo ldo -- -- 2v8 2v8 analog power analog power -- -- rf_1v5 rf_1v5 layout 4: layout 4: digital power digital power -- -- core_1v2 core_1v2 layout 5: layout 5: interface connect with interface connect with mt6238 mt6238 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 152 pcb component placement (1/3) pcb component placement (1/3) ldo tcxo saw filter external lna mt3326 the route of reference clock is the shortest to avoid interfering by other noise the capacitors close to analog and digital voltage output keep the rf path from antenna to mt3326 as short as possible free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 153 mt 3326 pcb component placement (2/3) pcb component placement (2/3) mt 3326 saw filter & external lna if the location of gps function block is far away from gps antenna pad, please place the first-stage saw filter and extern al lna close to gps antenna port for reducing rf path loss. good !! bad !! free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 154 gps antenna 12x12x7 active patch gsm antenna metal monopole on bottom. avoid gsm tx interfere with gps rx. 15mm clearance for triple band 25mm bt antenna metal pifa is recommended. it can be mounted on speaker holder. chip antenna is also an option. 90mm gnd length for triple band gps placement 10.5mmx10.4mm near gps antenna pen material is plastic near gsm ant. place gsm cal kit below pen. it occupy less gsm ant area. gps antenna placement (3/3) gps antenna placement (3/3) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 155 z probe-feed rhcp patch (fig.1) patch size: 12x12x4, 13x13x4 vendors: whayu, yageo, ci ro, microgate, amotech z probe-feed lp patch (fig.2) patch size: 15x10x4, 16x6x5 vendors: whayu, yageo, ci ro, microgate, amotech 12mm 12mm fig.1 10mm / 6mm 15mm / 16mm fig.2 proposal of gps patch antenna for slim phone proposal of gps patch antenna for slim phone 12x12x4 15x10x4 16x6x5 - 1 . 1 us d free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 156 pcb layout design note (1) pcb layout design note (1) ? rf part : ? rf path keep as short as possible fo r reducing rf signal transmitted loss. ? all rf traces have to do impedance control (50 ohm) for good sensitivity. ? rf traces route on the surface layer and far away from other high speed signal trace are recommended. ? isolate external lna input a nd output pin by copper plane. ? to keep the digital signal trace fa r away from the gps layout area. ? clear the metal below all matching componen t area to reduce the parasitic capacitance. clear the metal below the rf trace and pad !!! high parasitic capacitance couldn?t reach optimal rf match free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 157 ? tcxo part: ? keep tcxo clock trace as short as possible. ? keep the noisy traces far aw ay from tcxo clock traces. ? tcxo clock traces enclosed by pcb copper is recommended. ? position tcxo far away fr om any high temperature comp onent like as gsm_pa to avoid the frequency drift. pcb layout design note (2) pcb layout design note (2) mt3326 tcxo tcxo tcxo tcxo pin 11 tcxo clock input pin 46 gps signal input the best position : 1. clock trace is the shortest 2. it?s easy to route free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 158 ? power line part ? power trace should keep as low impedance and adequately add de -coupling capacitor for noise filtering . - recommended width of power trace : main trace: 20 mils at least branch into ic pin/ball: 10 mils at least ? keep de-coupling capacitors close to the power pin of gps chipset and external ldo. ? use many, many via holes to connect the power traces between layers. pcb layout design note (3) pcb layout design note (3) use many via holes to connect the power traces between layers free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 159 qualified vender list qualified vender list -- -- tcxo tcxo kyocera kyocera kt2520y16368acw28tma aurum tech inc. rakon it2205be 16.368 mhz tcxo 2520 (16.368 mhz ) epson toyocom epson toyocom tco-5869m tcxo (16.368 mhz) +/- 2.0ppm txc txc 7q16300001-16.368mhz ndk ndk eng3090b kyocera kyocera kt3225f16368acw28ta0 itti itti 1300269-16-16.368mhz epson toyocom epson toyocom tg-5005ce-21g unifirst enterprise tew tts14nsb-a8 aurum tech inc. rakon it3205be/it3205ce tcxo (16.368 mhz) +/- 0.5ppm vendor manufacturer part number component free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 160 m? toko tk71728 ame ame ame8801ceevz torex xc6215/xc6401 ldo_2v8 maxim maxim max2659 nec nec upc8231 ? jrc njg1117ha8 external lna vendor manufacturer part number component qualified vender list qualified vender list -- -- lna & ldo lna & ldo free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 161 qualified vender list qualified vender list -- -- gps antenna gps antenna size (mm 3 ) antenna vendor 13x13x4 amotech 12x12x4, 13x13x4, 15x15x4 ciro 15x15x4 mag.layers 12x12x4, 15x15x4 yageo 12x12x4, 13x13x4, 15x15x4 whayu circular-polarized patch free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 162 mt3326 hw debug sop mt3326 hw debug sop verify voltage level of all power supplies check connection of uart txd & rxd check gps hw configuration gpio setting & pmic 2.8v gps function ok! free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 163 mtk gps phone manufacture flow mtk gps phone manufacture flow assembly download ok? com port baud rate fw download single channel cnr current is good? conductive ate antenna multi- channel unit ttff and hot start are good? or open sky radiation minigps repair station pcba mt3326 no need !! mt3326 no need !! free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 164 mini gps tool (pc version) mini gps tool (pc version) ? feature gps status ttff test nmea output update rate baudrate waas log nmea 32 channel firmware ver. ? usage customers production line end users free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 165 test instruments (1/2) test instruments (1/2) multi-channel gps satellite simulation system spirent gss6560 spirent str4500 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 166 single channel gps-101 gps satellite simulator vna sa nfa areoflex sg test instruments (2/2) test instruments (2/2) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. dtv application note dtv application note free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 168 outline outline z dtv function block and reference design ? dtv function block ? dtv reference design z reference interface assignment and key component ? reference interface assignment ? key component z schematic and layout design guide ? schematic design guide ? layout design guide free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. dtv dtv function block and function block and reference design reference design free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 170 dtv function block z dtv solution consists of mt5151, mt5162 tuner and one low-power sdram. it's integrated in mcm tfbga-124 package to provide high integration level and high performance solution. z mtk dtv solution provides worldwide dvbt compliant standard in vhf and uhf reception via the common sdio/spi interface . silicon tuner silicon tuner ts demux ts demux i q agc tspd i2c demod & time slicing control demod & time slicing control mpe-fec mpe-fec cpu cpu i/q adc & rf interface i/q adc & rf interface time domain processing time domain processing freq. domain processing freq. domain processing fec fec host interface host interface memory controller memory controller low-power sdram low-power sdram tsif sdio spi free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 171 tp1213~1217 test pin f? ball ? , ?i t( s jtag_tck jtag_tdi jtag_tms jtag_tdo dtv_dvdd12 dtv_dvdd28 dtv_avdd12 dtv_avdd12 jtag_srst jtag_rtck jtag_rst# dtv_dvdd12 dtv_dvdd28 dtv_avdd28 dtv_vdd18 dtv_dvdd28 dtv_vdd18 dtv_dvdd12 rf_agc rf_agc_t dtv_dvdd28 dtv_vdd18 dtv_vdd18q rxd232a txd232a dtv_dvdd28 dtv_dvdd28 dtv_dvdd12 /mt5151_reset dtv_dvdd28 dtv_dvdd12 rf_agc_t rf_agc_t dtv_vdd18q dtv_vdd18q dtv_dvdd28 dtv_vdd18q rf_agc dtv_vdd18 txd232atxd232atxd232atxd232a jtag_tdo jtag_tdo jtag_tdo jtag_tdo jtag_tdo jtag_tdo jtag_tdo jtag_tdo /mt5151_reset vcc_rf dtv_vdd18q txd232atxd232a rxd232arxd232a 1 tp1201 tp30mil 1 tp1205 tp30mi l r1202 nc 0402 l1204 blm15eg121sn1 0402 c1298 27pf 0402 l1215 nc 0402 c1215 0.1uf 0402 2 3 4 1 5 6 j903 mm8130-2600b coaxial/con/mm8130-2600b c1235 5.6pf 0402 1 2 d801 esd1p0rfl in 1 gnd 2 gnd 3 out 4 gnd 5 u1202 lp92h (b8763) filter/smd/lp92a/epcos 1 tp1215 tp30mil c1239 0.1uf 0402 c1290 0.1uf 0402 l1210 lqw15an19ng00 0402 l1239 lqw15an82ng00 0402 r1234 1k 0402 1 tp1213 tp30mil r1233 1k 0402 1 tp1208 tp30mi l c1244 0.1uf 0402 c1299 6.8pf 0402 c1218 2.2uf 0603 c1224 0.1uf 0402 c1230 0.1uf 0402 vin 4 ce 1 vss 2 vout 3 u1200 xc6221a282nr ssot-24-4/xc6221 unbal 1 bal 2 bal 3 gnd 4 z1207 dlp11sn900hl2 l/choke/smd/dlp11sn c1237 100pf 0402 1 tp1206 tp30mi l c1251 47nf 0402 c1231 0.1uf 0402 r1211 100k 0402 l1218 15nh, 5%, lqw15a, wirewound 0402 r1231 12pf 0402 c1252 47nf 0402 c1123 1uf (x5r) 0402 c1236 12pf 0402 c1208 0.1uf 0402 dtv ant pad/1p/3.58x5.56 ant903 1 tp1211 tp30mi l c1205 0.1uf 0402 c1232 nc 0402 r1232 nc 0402 r1228 nc 0402 unbal 1 bal 2 bal 3 gnd 4 z1206 dlp11sn900hl2 l/choke/smd/dlp11sn l1214 lqw15an19ng00 0402 1 tp1209 tp30mi l l1213 lqw15an15ng00 0402 l1240 lqw15anr10j00 0402 c1240 100pf 0402 c1207 2.2uf 0603 c1216 0.1uf 0402 l1241 lqw15an33ng00 0402 c1214 0.1uf 0402 c1221 0.1uf 0402 r1225 4.7k 0402 1 tp1216 tp30mil r1226 6.8pf 0402 l1212 lqw15an13ng00 0402 l1219 nc 0402 1 tp1214 tp30mil l1211 blm15eg121sn1 0402 1 tp1207 tp30mi l r1227 lqw15an15ng00 0402 c1234 470nf 0402 vdd18q a13 vdd18q a15 vdd28 b16 rfn_l g15 rfp_l f16 gnd_rx1 f14 vcocreg k16 rfp_u h16 rfn_u j15 vdd_sx1 l15 vcoregout t14 vctrl r11 vcomon r13 demodclk_p n7 demodclk_n m8 pad_sdat m10 pad_sclt n9 qin k6 qip l5 iip j7 bbpga_ctrl_2 d10 bbpga_ctrl_1 e9 iin h6 wbpdout r7 atest p8 avss33_1 p6 vdd28 c15 vdd12 d16 vdd_rx1 e15 reset d14 rfvga_ctrl b14 dgnd c13 dgnd e13 gnd_rx1 g13 gnd_sx1 h14 vdd12 m16 gnd_sx1 m14 vdd28 n15 vdd28 p16 uart_tx n13 uart_rx p14 vdd12 r15 vdd18 t16 vdd_rx3 b12 vdd18q a11 vdd18 b10 dgnd c11 gnd_rx2 d12 gnd_rx2 e11 gnd_rx2 f12 gnd_rx3 f10 gnd_rx1 g11 gnd_sx2 h12 gnd_sx2 h10 gnd_rx3 g9 dgnd a9 dgnd c9 gnd_rx3 f8 gnd_rx3 h8 vdd18q b8 vdd18q a7 vdd28 b6 rf_agc a5 dgnd e5 gpio_data0 c5 gpio_data1 d6 gpio_data2 b4 gpio_data3 c7 gpio_data4 d8 gpio_data5 e7 gpio_data6 d4 gpio_data7 a3 gpio_data8 a1 gpio_data9 f6 gpio_data10 c3 vdd28 b2 sdio_cmd c1 sdio_clk d2 sdio_data_0 e1 sdio_data_1 e3 sdio_data_2 f2 sdio_data_3 g3 dgnd f4 vdd12 g1 vdd28 h2 ejtag_srst l1 ejtag_rtck k2 ejtag_tdo j3 ejtag_tdi g7 ejtag_tms g5 ejtag_tck j1 ej tag_tr st h4 reset_tuner j5 xta l p d k4 tspd _tu n er l3 digpd m4 vdd12 m2 dgnd n3 avss12_1 n1 avdd12_1 p2 avdd12_2 r1 xo c r e g t2 avss12_2 r3 xo r e g o u t p4 xtal_p t4 vdd_dig r5 looutp n5 looutn m6 avdd33_1 t6 gnd_dig l7 gnd_dig l9 gnd_rx3 k8 gnd_dig j9 xtal_32k t8 gnd_sx2 j11 gnd_sx3 k10 gnd_sx3 l11 vdd_sx2 t10 vdd18 r9 vdd28 p10 dgnd n11 dgnd m12 dgnd p12 vdd18 t12 u1201 mt5151 mcm tbga124(7x7)/b0.32/p0.4/smd c1245 100pf 0402 c1248 1000pf 0402 r1210 4.7k 0402 c1247 15pf 0402 c1225 0.1uf 0402 c1201 1uf 0603 c1204 0.1uf 0402 c1209 0.1uf 0402 1 tp1217 tp30mil 1 tp1200 tp30mil out 3 gnd 2 vcon 1 gnd 4 x1200 txc 26m tcxo3225 c1249 0.1uf 0402 c1253 0.5pf 0402 c1211 0.1uf 0402 c1227 2.2uf 0603 c1246 1000pf 0402 r1208 nc 0402 c1228 0.1uf 0402 1 tp1210 tp30mi l l1216 blm15eg121sn1 0402 l1217 33nh, 5%, lqw15a, wirewound 0402 r1230 33pf 0402 c1241 82pf 0402 c1243 82pf 0402 c1213 22pf 0402 c1233 1uf 0402 c1203 0.1uf 0402 vcc_rf vcc_rf vcc_rf vcc_rf dtv_avdd28 dtv_vdd18 dtv_dvdd12 dtv_vdd18 vcc_rf dtv_vdd18q dtv_ dvdd12 dtv_dvdd28 dtv_vdd18 dtv_dvdd28 dtv_dvdd28 dtv_vdd18 dtv_vdd18q dtv_avdd12 dtv_dvdd28 dtv_vdd18q dtv_dvdd12 dtv_dvdd28 dtv_dvdd28 vcc_rf dtv_avdd28 dtv_avdd12 dtv_dvdd12 dtv_1v2 dtv_2v8 dtv_2v8 dtv_1v8 vgp2 dtv_1v8 vcore2 dtv_1v2 vcc_pa vbat mc2c k 2, 5 mc2d a0 2, 5 mc2d a1 2, 5 mc2c m0 2, 5 rxd232a 4 txd232a 4 gpio121_dtv_pwr_en 2 gpio128 2 spi_miso 2,5 spi_mosi 2,5 close u1 uhf close u1 close u1 put more ground via between uhf network and vhf network sdio/spi mux pin to MT6516 ejtag debug pin (test pin ? ) dig out layer 2 of this xtal and layer 3 is solide ground sdio is mux pin with spi top_mode10 top_mode8 strap pin f? rfvga_ctrl ball f? rf_agc ball close u1 sam modified 12/19 vhf vhf power dtv reference design (dual-band: vhf & uhf) rf 2.8v ldo diplexer & ant matching 26m xtal uhf saw filter vhf band-select filter balun balun free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 172 tp1213~1217 test pin f? ball ? , ?i t( s jtag_tck jtag_tdi jtag_tms jtag_tdo dtv_dvdd12 dtv_dvdd28 dtv_avdd12 dtv_avdd12 jtag_srst jtag_rtck jtag_rst# dtv_dvdd12 dtv_dvdd28 dtv_avdd28 dtv_vdd18 dtv_dvdd28 dtv_vdd18 dtv_dvdd12 rf_agc rf_agc_t dtv_dvdd28 dtv_vdd18 dtv_vdd18q rxd232a txd232a dtv_dvdd28 dtv_dvdd28 dtv_dvdd12 /mt5151_reset dtv_dvdd28 dtv_dvdd12 rf_agc_t rf_agc_t dtv_vdd18q dtv_vdd18q dtv_dvdd28 dtv_vdd18q rf_agc dtv_vdd18 txd232atxd232atxd232atxd232a jtag_tdo jtag_tdo jtag_tdo jtag_tdo jtag_tdo jtag_tdo jtag_tdo jtag_tdo /mt5151_reset vcc_rf dtv_vdd18q txd 232atxd 232a rxd232arxd232a 1 tp1201 tp30mi l 1 tp1205 tp30mi l r1202 nc 0402 l1204 blm15eg121sn1 0402 l1215 nc 0402 c1215 0.1uf 0402 2 3 4 1 5 6 j903 mm8130-2600b coaxial/con/mm8130-2600b 1 2 d801 esd1p0rfl in 1 gnd 2 gnd 3 out 4 gnd 5 u1202 lp92h (b8763) filter/smd/lp92a/epcos 1 tp1215 tp30mi l c1239 0.1uf 0402 c1290 0.1uf 0402 l1210 lqw15an19ng00 0402 r1234 1k 0402 r1233 1k 0402 1 tp1213 tp30mi l c1244 0.1uf 0402 1 tp1208 tp30mi l c1218 2.2uf 0603 c1224 0.1uf 0402 c1230 0.1uf 0402 vin 4 ce 1 vss 2 vout 3 u1200 xc6221a282nr ssot-24-4/xc6221 1 tp1206 tp30mi l c1237 100pf 0402 c1251 47nf 0402 c1231 0.1uf 0402 r1211 100k 0402 c1252 47nf 0402 c1123 1uf (x5r) 0402 c1208 0.1uf 0402 dtv ant pad/1p/3.58x5.56 ant903 1 tp1211 tp30mi l c1205 0.1uf 0402 c1232 nc 0402 r1228 nc 0402 unbal 1 bal 2 bal 3 gnd 4 z1206 dlp11sn900hl2 l/choke/smd/dlp11sn 1 tp1209 tp30mi l l1214 lqw15an19ng00 0402 c1240 100pf 0402 c1216 0.1uf 0402 c1207 2.2uf 0603 c1221 0.1uf 0402 c1214 0.1uf 0402 r1225 4.7k 0402 1 tp1216 tp30mi l r1226 6.8pf 0402 l1212 lqw15an13ng00 0402 1 tp1214 tp30mi l l1211 blm15eg121sn1 0402 1 tp1207 tp30mi l r1227 lqw15an15ng00 0402 c1234 470nf 0402 vdd18q a13 vdd18q a15 vdd28 b16 rfn_l g15 rfp_l f16 gnd_rx1 f14 vcocreg k16 rfp_u h16 rfn_u j15 vdd_sx1 l15 vcoregout t14 vctrl r11 vcomon r13 demodclk_p n7 demodclk_n m8 pad_sdat m10 pad_sclt n9 qin k6 qip l5 iip j7 bbpga_ctrl_2 d10 bbpga_ctrl_1 e9 iin h6 wbpdout r7 atest p8 avss33_1 p6 vdd28 c15 vdd12 d16 vdd_rx1 e15 reset d14 rfvga_ctrl b14 dgnd c13 dgnd e13 gnd_rx1 g13 gnd_sx1 h14 vdd12 m16 gnd_sx1 m14 vdd28 n15 vdd28 p16 uart_tx n13 uart_rx p14 vdd12 r15 vdd18 t16 vdd_rx3 b12 vdd18q a11 vdd18 b10 dgnd c11 gnd_rx2 d12 gnd_rx2 e11 gnd_rx2 f12 gnd_rx3 f10 gnd_rx1 g11 gnd_sx2 h12 gnd_sx2 h10 gnd_rx3 g9 dgnd a9 dgnd c9 gnd_rx3 f8 gnd_rx3 h8 vdd18q b8 vdd18q a7 vdd28 b6 rf_agc a5 dgnd e5 gpio_data0 c5 gpio_data1 d6 gpio_data2 b4 gpio_data3 c7 gpio_data4 d8 gpio_data5 e7 gpio_data6 d4 gpio_data7 a3 gpio_data8 a1 gpio_data9 f6 gpio_data10 c3 vdd28 b2 sdio_cmd c1 sdio_clk d2 sdio_data_0 e1 sdio_data_1 e3 sdio_data_2 f2 sdio_data_3 g3 dgnd f4 vdd12 g1 vdd28 h2 ejtag_srst l1 ejtag_rtck k2 ejtag_tdo j3 ejtag_tdi g7 ejtag_tms g5 ejtag_tck j1 ejtag_trst h4 reset_tuner j5 xta l p d k4 tspd_tuner l3 digpd m4 vdd12 m2 dgnd n3 avss12_1 n1 avdd12_1 p2 avdd12_2 r1 xocreg t2 avss12_2 r3 xoregout p4 xta l _ p t4 vdd_dig r5 looutp n5 looutn m6 avdd33_1 t6 gnd_dig l7 gnd_dig l9 gnd_rx3 k8 gnd_dig j9 xtal_32k t8 gnd_sx2 j11 gnd_sx3 k10 gnd_sx3 l11 vdd_sx2 t10 vdd18 r9 vdd28 p10 dgnd n11 dgnd m12 dgnd p12 vdd18 t12 u1201 mt5151 mcm tbga124(7x7)/b0.32/p0.4/smd c1245 100pf 0402 r1210 4.7k 0402 c1225 0.1uf 0402 c1201 1uf 0603 c1204 0.1uf 0402 1 tp1217 tp30mi l c1209 0.1uf 0402 1 tp1200 tp30mi l out 3 gnd 2 vcon 1 gnd 4 x1 2 0 0 txc 26m tcxo3225 c1249 0.1uf 0402 c1211 0.1uf 0402 c1253 0.5pf 0402 c1227 2.2uf 0603 r1208 nc 0402 c1228 0.1uf 0402 l1216 blm15eg121sn1 0402 1 tp1210 tp30mi l c1241 82pf 0402 c1243 82pf 0402 c1233 1uf 0402 c1203 0.1uf 0402 vcc_rf vcc_rf vcc_rf vcc_rf dtv_avdd28 dtv_vdd18 dtv_dvdd12 dtv_vdd18 vcc_rf dtv_vdd18q dtv_dvdd12 dtv_dvdd28 dtv_vdd18 dtv_dvdd28 dtv_dvdd28 dtv_vdd18 dtv_vdd18q dtv_avdd12 dtv_dvdd28 dtv_vdd18q dtv_dvdd12 dtv_dvdd28 dtv_dvdd28 vcc_rf dtv_avdd28 dtv_avdd12 dtv_dvdd12 dtv_1v2 dtv_2v8 dtv_2v8 dtv_1v8 vgp2 dtv_1v8 vcore2 dtv_1v2 vcc_pa vbat mc 2c k 2, 5 mc2da0 2,5 mc2da1 2,5 mc 2c m0 2, 5 rxd232a 4 txd 232a 4 gpio121_dtv_pwr_en 2 gpio128 2 spi_miso 2,5 spi_mosi 2,5 close u1 uhf close u1 close u1 put more ground via between uhf network sdio/spi mux pin to MT6516 ejtag debug pin (test pin ? ) dig out layer 2 of this xtal and layer 3 is solide ground sdio is mux pin with spi top_mode10 top_mode8 strap pin f? rfvga_ctrl ball f? rf_agc ball close u1 power dtv reference design (uhf band only) rf 2.8v ldo 26m xtal uhf saw filter balun ant matching & rf connector delete vhf network for uhf band only free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. reference interface assignment and reference interface assignment and key component key component free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 174 reference interface assignment mt5151 bga sdio (4-bit) rstb 2.8v rf ldo ldo en pmu 2.8v 1.8v 1.2v example in MT6516 type pin function gpio128 rstb gpio121 ldo en mc0cm0 mc0da0 mc0da1 mc0da2 mc0da3 mc0ck gpio * ' sdio free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 175 key component z there are four key components on dvbt reference design, saw filter, crystal, balun, and high q wirewround inductor. l1212,l1210,l1214, l1239,l1241,l1240 l1213,l1217,l1218 murata lqw15a series inductor z1206, z1207 murata dlp11sn900hl2 balun x1200 ecera fl2600025 crystal u1202 epcos b8763 (lp92h) filter designator vendor part number item free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. schematic and layout design guide schematic and layout design guide free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 177 schematic design guide z the esd protection of rf input is poor, esd device should be added to protect rf circuit. z uhf saw filter & vhf hybrid filter should be added in rf path to filter out-band and gsm interference signal. z to ensure good performance, the frequency accuracy of crystal should meet +/- 30 ppm requirement with loading capacitance spec of 10pf. z in order to have better power noise immunity, rf 2.8v supply voltage is provided by stand-alone ldo. z io-2.8v and sdram-1.8v should be provided by linear regulation power. core-1.2v could be dc-dc power. z rf balun is strongly suggested to use for optimal rf performance free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 178 dtv layout guide ? 1/3 z dtv placement should keep away from gsm and cdma related circuits. z don't place dtv near noisy components , such as pmic, memory or other clock-wise/ high- swing signal. z rf trace of dtv should keep away from high speed signal , such as lcd and camera data bus. z to avoid any other noisy layout closer to rf ant port z put solid ground polygon and ground via surround layout area for metal casing. dtv MT6516 gsm pa gsm rf pmic bt+wlan gps free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 179 dtv layout guide ? 2/3 shielding case rf front-end z keep rf trace on same layer , don't use via on rf trace as possible as you can. z to avoid interference, use shielding case to cover dtv related circuits . z put rf balun as closer as possible to chip input. and make rou ting symmetrically. z put rf front-end routi ng in 50ohm trace and let those induct ors in orthogonal direction with each others. z place 2.8v rf ldo and crystal near to mt5151 as possible as you can. z dig out the copper plating under crystal pad output (pin3) to ch ip in inner layer . z rf trace should k eep 50ohm impedance and as short as possible. z place bypass capacitors close to power pin. z put dtv?s off-chip components surround by it in sequence to minimize rounting. z put rfagc in/ out r-c network as closer as possible to pin crystal rf balun bypass cap. c1203 bypass cap. c1209 bypass cap. c1214 bypass cap. c1204 bypass cap. c1230 rfagc in r-c rfagc out r-c free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 180 dtv layout guide ? 3/3 layer2 layer3 z as below shown, ma ke a dig-out clearance gap (>= 6mil) to cut ground plane from layer 2 to layer 6 to isolate rf and digital gnd. z dig out layer 2 ploy gon under rf front-end network start to cut gnd plane end to cut gnd plane dig-out dig-out balls inside this rf area: b16~p16;g15~n15;f14~m14; g13;d12~h12;e11~l11;f10~k10 ;g9~l9;f8~k8 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 181 reference layout ? 1/4 layer2 layer1 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 182 reference layout ? 2/4 layer4 layer3 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 183 reference layout ? 3/4 layer6 layer5 free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 184 reference layout ? 4/4 layer8 layer7 (other function placement instead of dtv) free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. www.mediatek.com free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. fm radio design guidelines fm radio design guidelines free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 187 mtk fm solution connection mtk fm solution connection mt6188 or mt6189cn mtk bb series (except mt6205) fm audio output system audio output control interface free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 188 fm design fm design free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 189 layout guidelines layout guidelines ? placement ? place the fm chip near the earphone jack. avoid high-speed digita l devices, such as memory devices, near the rf signal area. ? bypass cap for power should be placed beside the vccvco pin (mt6188 pin 9; mt6189 pin 13). ? routing ? fm antenna trace should have a 50 $ impedance. ? power should be routed to the bypass cap and the vccvco pin first, then to all other power pins on the fm chip. s ee the following pa ges for example. ? apply a single solid ground fo r all fm block ground signals. see the following pages for example. ? protect the following areas with gnd vias and planes: ? rf signal from the earphone ja ck all the way to the fm chip; ? 32.768 khz or 26 mhz signal; ? vco inductor (mt6188 pins 11,12; mt6189 pins 15,16); ? loop filter of mt6189 (connected to pin 17). free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 190 power feeding network layout guidelines power feeding network layout guidelines ? it is recommended to connect power of mt6189 and mt6188 sequentially, and placing the capacitance besi de vccvco. (examples below.) ? the fm power should be monopolized: do not connect other blocks to vcc_fm. vccvco vccst vdd vccrf bad mt6188 vccvco vdd vccrf vccst vccamp good mt6189 do not connec t to other blocks through fm block. this capacitor cannot be placed here. vccvco vdd vccrf good mt6188 vccst free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 191 ground layout ground layout ? ground gndvco, the loop filter, an d front-end matching on the same ground plane. ? using different ground planes connect ed by wire makes the fm signal susceptible to interference wi th another signals on the system. ? this rule is applicable for both mt6189 and mt6188: all gnd pins must be located on the same ground plane. bad mt6189 good mt6189 all ground pins are connected by wires. this design contains no ground plane. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 192 other system considerations for fm other system considerations for fm ? rule 1: protect the bb 32.768khz crystal layout ? if the 32.768khz signal is corrupted by digital signals, fm channel locking may be unstable . ? bb 32.768khz crystal layout rules: ? place the 32.768khz crystal unit clos e to the bb, and l2 beneath crystal needs to be complete ground. the crystal must be protected by ground vias and ground planes. ? do not route power, mcp, fm i2c traces near 32.768khz crystal unit. ? the 32.768khz traces between crystal uni t and bb should be on top layer. ? rule 2: backlight driver adoption ? use a charge pump backlight driver. ? do not use a dc-dc backlight driver in proj ects with fm application. doing so may cause increased noise leve ls when the backlight is on. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 193 audio interface design audio interface design ? 2.5mm/3.5mm earphone ? mini usb earphone free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 194 audio interface design guidelines audio interface design guidelines ? on earphone pins afl, afr, and mic: ?place 1 nf shunt capacitors (shunt to earphone gnd pin) closest to the earphone jack. to improve earphone echo performance, c onnect the 3 capacitors from each pin to the earphone gnd pin separately. (see next page.) ? place the blm18bd252sn1 series bead second closest to the earphone jack. ? no other components can be closer to the earphone jack. ? place a series 150 nh inductor on earphone gnd pin as antenna matching. ? earphone gnd wire (fm_ant) should not be connected to the earphone connector shell. ? an earphone longer than 150 cm is recommended for better performance. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 195 fm_ant mic e-l e-r others fm tuner mt6188 matching inductor pcb earphone earphone connector 22uh earphone_gnd mic e-l e-r nc l r mic audio interface design concept audio interface design concept add caps on l, r paths, to provide extra path for fm. add beads on headset related pins, to avoid interference (or bypass) path. these beads should be placed as close to the phone jack as possible. this point is the earphone gnd. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 196 1~2 db earphone length > 150 cm 2~3 db 1 nf shunt cap bet ween earphone afl, afr, mic, and gnd pins 14.5 db series beads on earphone afl, afr, and mic pins improvement amount wireless sensitivity enhancement wireless sensitivity enhancement ? each earphone suggestions improves wireless sensitivity significantly. the following table shows the improvement amount based on mtk?s experiments. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 197 2.5mm/3.5mm earphone design 2.5mm/3.5mm earphone design free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 198 c402 1nf 1 2 c403 1nf 1 2 np_nc1 np_nc2 j401 mini_jack_6p 7 8 1 3 5 2 6 4 fm_ant {1} esd400 vce . 1 . 2 esd401 vce . 1 . 2 esd402 vce . 1 . 2 xmicp c404 33pf 1 2 l101 22uh 2 1 c405 33pf 1 2 b402 2500 ohm @ 100 mhz 2 1 b403 2500 ohm @ 100 mhz 2 1 l101 150nh 2 1 xspk_l b401 2500 ohm @ 100 mhz 2 1 xspk_r xspk_l c401 1nf 1 2 xspk_r audio interface reference circuit audio interface reference circuit (2.5mm or 3.5mm earphone jack) (2.5mm or 3.5mm earphone jack) add beads on these lines. these beads should be placed as close to the earphone jack as possible. to audio amp, mic circuits these caps cannot be closer to the earphone jack than the beads. series 150 nh inductor for antenna matching. shunt these earphone lines with 1nf caps. connect this 22uh inductor to mobile phone ground. blm18bd252sn1 blm18bd252sn1 can be used instead of a 22 uh inductor. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 199 mini usb earphone design mini usb earphone design ? with only 1 gnd pin on io connector ? with 2 gnd pins on io connector free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 200 these 4 pins are directly connected to pcb ground. do not connect these pins to the gnd/fm_ant pin. 4 outer shell pins of the io connector. mainly used for better connector strength. can also serve as charger gnd. mech_gnd cannot be directly connected to pcb ground. must be connected to pcb ground through a 22uh inductor. gnd for all mini usb accessories and fm antenna. gnd/fm ant notes for pcb design function io pin name io connector pin description earphone gnd wire connection. charger gnd wire connection. charger: connect these pins. earphone: do not connect these pins. mini usb io connector design recommendation: mini usb io connector design recommendation: only 1 gnd pin on io connector only 1 gnd pin on io connector accessory interior design suggestion ? the earphone gnd wire must be used for the fm antenna. inside the earphone, the gnd wire cannot be connected to any other wire or to the oute r shell in any way. other wires inside the earphone cannot be connected to pcb gnd. ? the 22uh inductor c annot tolerate high current. for high current application, such as a charger, connect the charger gnd wire inside the charger to both the gnd/fm_ant pin and the charger outer shell. ? in this example, the earphone gnd wire is connected to io connector pin6, and the charger gnd wire is connected to pin6 and the charger outer shell. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 201 mp3_outl0 esd203 1 1 2 2 t204 vce . 1 . 2 mp3_outr0 r210 33r l202 22uh r209 33r l201 150nh io200 mini usb 10 pin plug nc 1 mp3_outl 2 mp3_outr 3 utxd1 4 urxd1 5 gnd/fm_ant 6 mic_in 7 usb_dm 8 usb_dp 9 vchg 10 mech_gnd 11 mech_gnd 12 mech_gnd 13 mech_gnd 14 esd201 1 1 2 2 esd203 1 1 2 2 esd210 1 1 2 2 mic0 c225 1nf t211 . 1 . 2 t205 vce . 1 . 2 t204 vce . 1 . 2 vchg l204 blm18bd252sn1 l205 blm18bd252sn1 l206 blm18bd252sn1 fm_ant c223 1nf c224 1nf usb_dp0 usb_dm0 utxd1 urxd1 connect this 22uh inductor to mobile phone ground. series 150 nh inductor for antenna matching. shunt these earphone line s with 1nf caps. add beads on thes e lines. these beads should be placed as close to the earphone jack as possible . these caps cannot be closer to the earphone jack than the beads. to audio amp, mic circuits audio interface reference circuit: audio interface reference circuit: only 1 gnd pin on io connector only 1 gnd pin on io connector free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 202 accessory interior design suggestion ? the earphone gnd wire must be used for the fm antenna. inside the earphone, the gnd wire cannot be connected to any other wire or to the outer shell in any wa y. other wires inside the earphone cannot be connected to pcb gnd. ? the 22uh inductor c annot tolerate high current. for high current applications, such as a charger, use another io connector pin if available. the charger gnd wire inside the charger can also be connected to the charger outer shell. ? in this example, the earphone gnd wire is connected to io connector pin6, and the charger gnd wire is connected to pin1 and possibly the c harger outer shell as well. these 4 pins are directly connected to pcb ground. do not connect these pins to ear_gnd/fm_ant. 4 outer shell pins of the io connector. mainly used for better connector strength. can also be served as charger gnd. mech_gnd this pin is directly connected to pcb ground. do not connect this pin to the ear_gnd/fm_ant pin. gnd for mini usb accessory, with large gnd current. ckt_gnd cannot be directly connected to pcb ground. must be connected to pcb ground through a 22uh inductor. earphone gnd, also fm antenna. ear_gnd/fm_ant note for pcb design function io pin name earphone gnd wire connection charger gnd wire connection inside earphone, do not connect these pins. io connector pin description mini usb io connector design recommendation: mini usb io connector design recommendation: 2 gnd pins on io connector 2 gnd pins on io connector free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 203 mp3_outl0 esd203 1 1 2 2 t204 vce . 1 . 2 mp3_outr0 r210 33r l202 22uh r209 33r l201 150nh io200 mini usb 10 pin plug ckt_gnd 1 mp3_outl 2 mp3_outr 3 utxd1 4 urxd1 5 gnd/fm_ant 6 mic_in 7 usb_dm 8 usb_dp 9 vchg 10 mech_gnd 11 mech_gnd 12 mech_gnd 13 mech_gnd 14 esd201 1 1 2 2 esd203 1 1 2 2 esd210 1 1 2 2 mic0 c225 1nf t211 . 1 . 2 t205 vce . 1 . 2 t204 vce . 1 . 2 vchg l204 blm18bd252sn1 l205 blm18bd252sn1 l206 blm18bd252sn1 fm_ant c223 1nf c224 1nf usb_dp0 usb_dm0 utxd1 urxd1 connect this 22uh inductor to mobile phone ground. series 150 nh inductor for antenna matching. these caps cannot be closer to the earphone jack than the beads. to audio amp, mic circuits shunt these earphone lines with 1nf caps. add beads on these lines. these beads should be pla ced as close to the earphone jack as possible. audio interface reference circuit: audio interface reference circuit: 2 gnd pins on io connector 2 gnd pins on io connector free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 204 ? series beads on earphone pins afl, afr, and mic ? suggested: 0603 0603 - - size blm18bd252sn1 bead size blm18bd252sn1 bead however, if board space is limite d, 0402-size bead blm15bd182sn1 or blm15hd182sn1 can be used instead. ? inductor connecting earphone gnd wire to board gnd ? suggested: 22 22 uh uh inductor inductor or blm18bd252sn1 bead blm18bd252sn1 bead however, if the earphone gnd pin se rves as the only gnd path for the charger, then this component must be able to tolerate high current. the components in the table below can be used instead. usable, but its wireless performance is the worst among the three. not recommended unless such a high current is required. 1100 ma 100 mhz 0805 0.47 uh lqm21pnr47mc0d 800 ma 90 mhz 0805 1.0 uh lqm21pn1r0mc0d 485 ma 100 mhz 0603 1.0 uh lqh2mcn1r0m02 notes rated current self-resonant frequency size inductor value murata part number component replacement suggestions component replacement suggestions free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 205 fm design checklist fm design checklist follow the fm system layout guide. 5 mt6189 projects only : a high q inductor is used (for the 15 nh vco inductor). 7 mini usb earphones : follow mtk?s suggestion for gnd connection on pcb and inside earphone. 8 the fm antenna path is routed using a 50 $ rf trace, and a 150 nh inductor is used for antenna matching. 6 the vcc bypass cap is placed beside the vccvco pin, an d the vcc feeding network routed is properly. 4 the earphone is longer than 150 cm. 3 1 nf shunt caps are placed between the af l, afr, mic, and gnd pins of the earphone jack. 2 series beads are placed on the afl, af r, and mic pins of the earphone jack. 1 checkpoint done! item if you require mtk?s assistance in fm design, please prepare this checklist and submit it along with schematics , layout files and earphone schema tics/data sheet . free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 206 more detailed fm earphone more detailed fm earphone antenna illustrations antenna illustrations ? illustration of fm earphone antenna ? fm earphone antenna pin definition ? fm earphone antenna troubleshooting free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 207 illustration of fm earphone antenna (1/2) illustration of fm earphone antenna (1/2) ? on next page, there is an illustration to explain the respective purposes of each components. it can help customers to know how to enhance fm wireless performance. ? besides fm schematics, wrong earphone pin definition also destroys fm wireless performance . ? notice that the only one path from earphone_gnd to pcb_gnd is via fm_ant pin and 22uh . if there are another paths exis ting, fm receiving signal would degrade seriously. this issues frequently happens on customers? projects. ? four pins are enough on earphone incl uding r, l, mic, and earphone_gnd. ? only earphone_gnd can be used as fm antenna. ? place all fm related components near earphone jack in pcb layout. free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 208 illustration of fm earphone antenna (2/2) illustration of fm earphone antenna (2/2) 5. earphone length earphone length 165 cm is recommended. 4. 150 150 nh nh earphone antenna matching 3. 22 22 uh uh earphone gnd connects to pcb gnd only via this 22 uh. rf choke @100mhz 5 2 1 3 4 2. parallel 1.0 parallel 1.0 nf nf cap_short cap_short @100mhz @100mhz conduct fm signal to fm i nput from r, l, and mic traces. fm receiving signal can be enhanced. 1. serial beads 2.5 serial beads 2.5 kohm kohm @100mhz @100mhz avoid fm signal loss through r, l, and mic traces. fm_ant mic e-l e-r others fm tuner mt6188 150 nh earphone connector 22uh earphone_gnd mic e-l e-r nc l r mic earphone pcb 50 ohm free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 209 fm earphone antenna pin definition (1/3) fm earphone antenna pin definition (1/3) ? the following illustrates the correct pin definition for the fm earphone antenna: fm_ant mic e-l e-r pcb_gnd others earphone connector earphone_gnd mic e-l e-r nc earphone pcb free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 210 fm earphone antenna pin definition (2/3) fm earphone antenna pin definition (2/3) ? some incorrect pin definitions ? case 1: floating fm_ant pin ? case 2: earphone_gnd connects to both fm_ant pin and pcb_gnd fm_ant mic e-l e-r pcb_gnd others mic e-l e-r earphone_gnd earphone pcb fm_ant mic e-l e-r pcb_gnd others earphone_gnd mic e-l e-r gnd earphone pcb free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 211 fm earphone antenna pin definition (3/3) fm earphone antenna pin definition (3/3) ? some incorrect pin definitions ? case 3: unnecessary gnd pin used on the earphone side ? case 4: unnecessary signal pins used on the earphone side fm_ant mic e-l e-r pcb_gnd others earphone_gnd mic e-l e-r gnd earphone pcb fm_ant mic e-l e-r pcb_gnd others earphone_gnd mic e-l e-r others earphone pcb free datasheet http://www.datasheet-pdf.com/ copyright ? mediatek inc. all rights reserved. 212 case 1 short open open case 2 short short short correct open open short issue pcb_gnd to earphone_gnd fm_ant to pcb_gnd fm_ant to earphone_gnd fm earphone antenna troubleshooting fm earphone antenna troubleshooting ? simple troubleshooting techniques: a. check that only four earphone pins are used. ( case 3 , case 4 ) b. remove the 22 uh inductor. c. plug in the earphone. d. use a digital multimeter to check whether the connections between pcb_gnd , fm_ant pin, and earphone_gnd pin are open or short . free datasheet http://www.datasheet-pdf.com/ |
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